From 09c7f4026afa46ca7ca67d47179013a340a5e944 Mon Sep 17 00:00:00 2001 From: Daniel Sanders Date: Wed, 23 Oct 2013 10:36:52 +0000 Subject: [PATCH] [mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193239 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/MipsMSAInstrInfo.td | 22 +++++-- lib/Target/Mips/MipsSEISelLowering.cpp | 70 +++++++++++++++++++++++ lib/Target/Mips/MipsSEISelLowering.h | 6 ++ test/CodeGen/Mips/msa/arithmetic_float.ll | 69 ++++++++++++++++++++++ 4 files changed, 163 insertions(+), 4 deletions(-) diff --git a/lib/Target/Mips/MipsMSAInstrInfo.td b/lib/Target/Mips/MipsMSAInstrInfo.td index b93b5c7dd5d..492e82830af 100644 --- a/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/lib/Target/Mips/MipsMSAInstrInfo.td @@ -315,6 +315,9 @@ def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), (sub node:$wd, (mul node:$ws, node:$wt))>; +def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), + (fmul node:$ws, (fexp2 node:$wt))>; + // Immediates def immSExt5 : ImmLeaf(Imm);}]>; def immSExt10: ImmLeaf(Imm);}]>; @@ -1811,10 +1814,19 @@ class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; -class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", int_mips_fexp2_w, - MSA128WOpnd>; -class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", int_mips_fexp2_d, - MSA128DOpnd>; +// The fexp2.df instruction multiplies the first operand by 2 to the power of +// the second operand. We therefore need a pseudo-insn in order to invent the +// 1.0 when we only need to match ISD::FEXP2. +class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; +class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; +let usesCustomInserter = 1 in { + class FEXP2_W_1_PSEUDO_DESC : + MipsPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), + [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; + class FEXP2_D_1_PSEUDO_DESC : + MipsPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), + [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; +} class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, MSA128WOpnd, MSA128HOpnd>; @@ -2757,6 +2769,8 @@ def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC; def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC; def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC; +def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC; +def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC; def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC; def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC; diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp index def8957632b..6c89424eb6a 100644 --- a/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/lib/Target/Mips/MipsSEISelLowering.cpp @@ -220,6 +220,7 @@ addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { setOperationAction(ISD::FABS, Ty, Legal); setOperationAction(ISD::FADD, Ty, Legal); setOperationAction(ISD::FDIV, Ty, Legal); + setOperationAction(ISD::FEXP2, Ty, Legal); setOperationAction(ISD::FLOG2, Ty, Legal); setOperationAction(ISD::FMA, Ty, Legal); setOperationAction(ISD::FMUL, Ty, Legal); @@ -840,6 +841,10 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, return emitFILL_FW(MI, BB); case Mips::FILL_FD_PSEUDO: return emitFILL_FD(MI, BB); + case Mips::FEXP2_W_1_PSEUDO: + return emitFEXP2_W_1(MI, BB); + case Mips::FEXP2_D_1_PSEUDO: + return emitFEXP2_D_1(MI, BB); } } @@ -1332,6 +1337,13 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, // an equivalent v4i32. return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); } + case Intrinsic::mips_fexp2_w: + case Intrinsic::mips_fexp2_d: { + EVT ResTy = Op->getValueType(0); + return DAG.getNode( + ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), + DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); + } case Intrinsic::mips_flog2_w: case Intrinsic::mips_flog2_d: return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); @@ -2506,3 +2518,61 @@ MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; } + +// Emit the FEXP2_W_1 pseudo instructions. +// +// fexp2_w_1_pseudo $wd, $wt +// => +// ldi.w $ws, 1 +// fexp2.w $wd, $ws, $wt +MachineBasicBlock * +MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Mips::MSA128WRegClass; + unsigned Ws1 = RegInfo.createVirtualRegister(RC); + unsigned Ws2 = RegInfo.createVirtualRegister(RC); + DebugLoc DL = MI->getDebugLoc(); + + // Splat 1.0 into a vector + BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); + BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); + + // Emit 1.0 * fexp2(Wt) + BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) + .addReg(Ws2) + .addReg(MI->getOperand(1).getReg()); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +// Emit the FEXP2_D_1 pseudo instructions. +// +// fexp2_d_1_pseudo $wd, $wt +// => +// ldi.d $ws, 1 +// fexp2.d $wd, $ws, $wt +MachineBasicBlock * +MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, + MachineBasicBlock *BB) const { + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Mips::MSA128DRegClass; + unsigned Ws1 = RegInfo.createVirtualRegister(RC); + unsigned Ws2 = RegInfo.createVirtualRegister(RC); + DebugLoc DL = MI->getDebugLoc(); + + // Splat 1.0 into a vector + BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); + BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); + + // Emit 1.0 * fexp2(Wt) + BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) + .addReg(Ws2) + .addReg(MI->getOperand(1).getReg()); + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} diff --git a/lib/Target/Mips/MipsSEISelLowering.h b/lib/Target/Mips/MipsSEISelLowering.h index c20cbffbb21..c5210d94b34 100644 --- a/lib/Target/Mips/MipsSEISelLowering.h +++ b/lib/Target/Mips/MipsSEISelLowering.h @@ -102,6 +102,12 @@ namespace llvm { /// \brief Emit the FILL_FD pseudo instruction MachineBasicBlock *emitFILL_FD(MachineInstr *MI, MachineBasicBlock *BB) const; + /// \brief Emit the FEXP2_W_1 pseudo instructions. + MachineBasicBlock *emitFEXP2_W_1(MachineInstr *MI, + MachineBasicBlock *BB) const; + /// \brief Emit the FEXP2_D_1 pseudo instructions. + MachineBasicBlock *emitFEXP2_D_1(MachineInstr *MI, + MachineBasicBlock *BB) const; }; } diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll index 4392c77213f..43a1f29fc7f 100644 --- a/test/CodeGen/Mips/msa/arithmetic_float.ll +++ b/test/CodeGen/Mips/msa/arithmetic_float.ll @@ -236,6 +236,73 @@ define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind { ; CHECK: .size fabs_v2f64 } +define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind { + ; CHECK: fexp2_v4f32: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1) + ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: ffint_u.w [[R4:\$w[0-9]+]], [[R3]] + ; CHECK-DAG: fexp2.w [[R4:\$w[0-9]+]], [[R3]], [[R1]] + store <4 x float> %2, <4 x float>* %c + ; CHECK-DAG: st.w [[R4]], 0($4) + + ret void + ; CHECK: .size fexp2_v4f32 +} + +define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind { + ; CHECK: fexp2_v2f64: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1) + ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1 + ; CHECK-DAG: ffint_u.d [[R4:\$w[0-9]+]], [[R3]] + ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]] + store <2 x double> %2, <2 x double>* %c + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size fexp2_v2f64 +} + +define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind { + ; CHECK: fexp2_v4f32_2: + + %1 = load <4 x float>* %a + ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5) + %2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1) + %3 = fmul <4 x float> , %2 + ; CHECK-DAG: lui [[R3:\$[0-9]+]], 16384 + ; CHECK-DAG: fill.w [[R4:\$w[0-9]+]], [[R3]] + ; CHECK-DAG: fexp2.w [[R5:\$w[0-9]+]], [[R4]], [[R1]] + store <4 x float> %3, <4 x float>* %c + ; CHECK-DAG: st.w [[R5]], 0($4) + + ret void + ; CHECK: .size fexp2_v4f32_2 +} + +define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind { + ; CHECK: .8byte 4611686018427387904 + ; CHECK-NEXT: .8byte 4611686018427387904 + ; CHECK: fexp2_v2f64_2: + + %1 = load <2 x double>* %a + ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5) + %2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1) + %3 = fmul <2 x double> , %2 + ; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], %lo( + ; CHECK-DAG: fexp2.d [[R4:\$w[0-9]+]], [[R3]], [[R1]] + store <2 x double> %3, <2 x double>* %c + ; CHECK-DAG: st.d [[R4]], 0($4) + + ret void + ; CHECK: .size fexp2_v2f64_2 +} + define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind { ; CHECK: fsqrt_v4f32: @@ -378,6 +445,8 @@ define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind { declare <4 x float> @llvm.fabs.v4f32(<4 x float> %Val) declare <2 x double> @llvm.fabs.v2f64(<2 x double> %Val) +declare <4 x float> @llvm.exp2.v4f32(<4 x float> %val) +declare <2 x double> @llvm.exp2.v2f64(<2 x double> %val) declare <4 x float> @llvm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) declare <2 x double> @llvm.fma.v2f64(<2 x double> %a, <2 x double> %b,