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Use divide single for 32 bit signed divides
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76010 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -636,17 +636,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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switch (Opcode) {
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default: break;
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case ISD::SDIVREM: {
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unsigned Opc, MOpc, ClrOpc = 0;
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unsigned Opc, MOpc;
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SDValue N0 = Node->getOperand(0);
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SDValue N1 = Node->getOperand(1);
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MVT ResVT;
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bool is32Bit = false;
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switch (NVT.getSimpleVT()) {
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default: assert(0 && "Unsupported VT!");
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case MVT::i32:
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Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
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ClrOpc = SystemZ::MOV64Pr0_even;
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ResVT = MVT::v2i32;
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ResVT = MVT::v2i64;
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is32Bit = true;
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break;
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case MVT::i64:
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Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m;
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@ -658,7 +659,11 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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bool foldedLoad = TryFoldLoad(Op, N1, Tmp0, Tmp1, Tmp2);
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// Prepare the dividend
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SDNode *Dividend = N0.getNode();
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SDNode *Dividend;
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if (is32Bit)
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Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0);
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else
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Dividend = N0.getNode();
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// Insert prepared dividend into suitable 'subreg'
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SDNode *Tmp = CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF,
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@ -668,10 +673,6 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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SDValue(Tmp, 0), SDValue(Dividend, 0),
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CurDAG->getTargetConstant(subreg_odd, MVT::i32));
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// Zero out even subreg, if needed
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if (ClrOpc)
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Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
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SDNode *Result;
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SDValue DivVal = SDValue(Dividend, 0);
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if (foldedLoad) {
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@ -686,10 +687,16 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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// Copy the division (odd subreg) result, if it is needed.
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if (!Op.getValue(0).use_empty()) {
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SDNode *Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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dl, (is32Bit ? MVT::v2i32 : MVT::i64),
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_odd,
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MVT::i32));
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if (is32Bit)
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Div = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Div, 0),
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CurDAG->getTargetConstant(subreg_32bit,
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MVT::i32));
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ReplaceUses(Op.getValue(0), SDValue(Div, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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@ -701,10 +708,17 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) {
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// Copy the remainder (even subreg) result, if it is needed.
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if (!Op.getValue(1).use_empty()) {
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SDNode *Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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dl, (is32Bit ? MVT::v2i32 : MVT::i64),
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SDValue(Result, 0),
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CurDAG->getTargetConstant(subreg_even,
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MVT::i32));
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if (is32Bit)
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Rem = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
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dl, NVT,
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SDValue(Rem, 0),
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CurDAG->getTargetConstant(subreg_32bit,
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MVT::i32));
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ReplaceUses(Op.getValue(1), SDValue(Rem, 0));
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#ifndef NDEBUG
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DOUT << std::string(Indent-2, ' ') << "=> ";
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@ -588,8 +588,8 @@ def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
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"msgfr\t{$dst, $src2}",
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[(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
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def SDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
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"dr\t{$dst, $src2}",
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def SDIVREM32r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
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"dsgfr\t{$dst, $src2}",
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[]>;
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def SDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dsgr\t{$dst, $src2}",
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@ -602,8 +602,8 @@ def UDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
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"dlgr\t{$dst, $src2}",
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[]>;
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let mayLoad = 1 in {
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def SDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
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"d\t{$dst, $src2}",
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def SDIVREM32m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
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"dsgf\t{$dst, $src2}",
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[]>;
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def SDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
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"dsg\t{$dst, $src2}",
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