From 09e460662a8d7328da1b938d5581a6ef3740b51d Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 5 Sep 2006 02:31:13 +0000 Subject: [PATCH] Completely eliminate def&use operands. Now a register operand is EITHER a def operand or a use operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30109 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/CodeGen/MachineInstr.h | 56 ++++--------------- include/llvm/CodeGen/MachineInstrBuilder.h | 16 ++---- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 16 +++--- lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 8 +-- lib/Target/ARM/ARMRegisterInfo.cpp | 4 +- lib/Target/Alpha/AlphaRegisterInfo.cpp | 44 +++++++++------ lib/Target/IA64/IA64RegisterInfo.cpp | 26 ++++----- lib/Target/PowerPC/PPCRegisterInfo.cpp | 6 +- lib/Target/Sparc/SparcRegisterInfo.cpp | 4 +- lib/Target/X86/X86RegisterInfo.cpp | 4 +- 10 files changed, 78 insertions(+), 106 deletions(-) diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h index c3ad83c5225..a205792e477 100644 --- a/include/llvm/CodeGen/MachineInstr.h +++ b/include/llvm/CodeGen/MachineInstr.h @@ -38,26 +38,6 @@ template struct ilist; // Representation of each machine instruction operand. // struct MachineOperand { -private: - // Bit fields of the flags variable used for different operand properties - enum { - DEFFLAG = 0x01, // this is a def of the operand - USEFLAG = 0x02 // this is a use of the operand - }; - -public: - // UseType - This enum describes how the machine operand is used by - // the instruction. Note that the MachineInstr/Operator class - // currently uses bool arguments to represent this information - // instead of an enum. Eventually this should change over to use - // this _easier to read_ representation instead. - // - enum UseType { - Use = USEFLAG, /// only read - Def = DEFFLAG, /// only written - UseAndDef = Use | Def /// read AND written - }; - enum MachineOperandType { MO_Register, // Register operand. MO_Immediate, // Immediate Operand @@ -78,8 +58,8 @@ private: int64_t immedVal; // For MO_Immediate and MO_*Index. } contents; - char flags; // see bit field definitions above - MachineOperandType opType:8; // Pack into 8 bits efficiently after flags. + MachineOperandType opType:8; // Discriminate the union. + bool IsDef : 1; // True if this is a def, false if this is a use. /// offset - Offset to address of global or external, only valid for /// MO_GlobalAddress, MO_ExternalSym and MO_ConstantPoolIndex @@ -95,7 +75,7 @@ public: const MachineOperand &operator=(const MachineOperand &MO) { contents = MO.contents; - flags = MO.flags; + IsDef = MO.IsDef; opType = MO.opType; offset = MO.offset; return *this; @@ -105,10 +85,6 @@ public: /// MachineOperandType getType() const { return opType; } - /// getUseType - Returns the MachineOperandUseType of this operand. - /// - UseType getUseType() const { return UseType(flags & (USEFLAG|DEFFLAG)); } - /// Accessors that tell you what kind of MachineOperand you're looking at. /// bool isReg() const { return opType == MO_Register; } @@ -167,13 +143,10 @@ public: return contents.SymbolName; } - /// MachineOperand methods for testing that work on any kind of - /// MachineOperand... - /// - bool isUse() const { return flags & USEFLAG; } - bool isDef() const { return flags & DEFFLAG; } - MachineOperand &setUse() { flags |= USEFLAG; return *this; } - MachineOperand &setDef() { flags |= DEFFLAG; return *this; } + bool isUse() const { return !IsDef; } + bool isDef() const { return IsDef; } + void setIsUse() { IsDef = false; } + void setIsDef() { IsDef = true; } /// getReg - Returns the register number. /// @@ -216,9 +189,10 @@ public: /// ChangeToRegister - Replace this operand with a new register operand of /// the specified value. If an operand is known to be an register already, /// the setReg method should be used. - void ChangeToRegister(unsigned Reg) { + void ChangeToRegister(unsigned Reg, bool isDef) { opType = MO_Register; contents.RegNo = Reg; + IsDef = isDef; } friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop); @@ -307,11 +281,10 @@ public: /// addRegOperand - Add a register operand. /// - void addRegOperand(unsigned Reg, - MachineOperand::UseType UTy = MachineOperand::Use) { + void addRegOperand(unsigned Reg, bool IsDef) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_Register; - Op.flags = UTy; + Op.IsDef = IsDef; Op.contents.RegNo = Reg; Op.offset = 0; } @@ -322,7 +295,6 @@ public: void addImmOperand(int64_t Val) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_Immediate; - Op.flags = 0; Op.contents.immedVal = Val; Op.offset = 0; } @@ -330,7 +302,6 @@ public: void addMachineBasicBlockOperand(MachineBasicBlock *MBB) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_MachineBasicBlock; - Op.flags = 0; Op.contents.MBB = MBB; Op.offset = 0; } @@ -340,7 +311,6 @@ public: void addFrameIndexOperand(unsigned Idx) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_FrameIndex; - Op.flags = 0; Op.contents.immedVal = Idx; Op.offset = 0; } @@ -351,7 +321,6 @@ public: void addConstantPoolIndexOperand(unsigned Idx, int Offset) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_ConstantPoolIndex; - Op.flags = 0; Op.contents.immedVal = Idx; Op.offset = Offset; } @@ -362,7 +331,6 @@ public: void addJumpTableIndexOperand(unsigned Idx) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_JumpTableIndex; - Op.flags = 0; Op.contents.immedVal = Idx; Op.offset = 0; } @@ -370,7 +338,6 @@ public: void addGlobalAddressOperand(GlobalValue *GV, int Offset) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_GlobalAddress; - Op.flags = 0; Op.contents.GV = GV; Op.offset = Offset; } @@ -380,7 +347,6 @@ public: void addExternalSymbolOperand(const char *SymName) { MachineOperand &Op = AddNewOperand(); Op.opType = MachineOperand::MO_ExternalSymbol; - Op.flags = 0; Op.contents.SymbolName = SymName; Op.offset = 0; } diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h index 0d4d07d00a5..3a1335a1593 100644 --- a/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/include/llvm/CodeGen/MachineInstrBuilder.h @@ -33,10 +33,8 @@ public: /// addReg - Add a new virtual register operand... /// - const MachineInstrBuilder &addReg( - int RegNo, - MachineOperand::UseType Ty = MachineOperand::Use) const { - MI->addRegOperand(RegNo, Ty); + const MachineInstrBuilder &addReg(int RegNo, bool isDef = false) const { + MI->addRegOperand(RegNo, isDef); return *this; } @@ -92,12 +90,10 @@ inline MachineInstrBuilder BuildMI(int Opcode, unsigned NumOperands) { /// destination virtual register. NumOperands is the number of additional add* /// calls that are expected, not including the destination register. /// -inline MachineInstrBuilder BuildMI( - int Opcode, unsigned NumOperands, - unsigned DestReg, - MachineOperand::UseType useType = MachineOperand::Def) { +inline MachineInstrBuilder +BuildMI(int Opcode, unsigned NumOperands, unsigned DestReg) { return MachineInstrBuilder(new MachineInstr(Opcode, NumOperands+1)) - .addReg(DestReg, useType); + .addReg(DestReg, true); } /// BuildMI - This version of the builder inserts the newly-built @@ -112,7 +108,7 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, unsigned DestReg) { MachineInstr *MI = new MachineInstr(Opcode, NumOperands+1); BB.insert(I, MI); - return MachineInstrBuilder(MI).addReg(DestReg, MachineOperand::Def); + return MachineInstrBuilder(MI).addReg(DestReg, true); } /// BuildMI - This version of the builder inserts the newly-built diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index d33e1ecef7e..71f2bce118f 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -255,11 +255,11 @@ static unsigned CreateVirtualRegisters(const MRegisterInfo *MRI, // the machine instruction. unsigned ResultReg = RegMap->createVirtualRegister(getInstrOperandRegClass(MRI, TII, &II, 0)); - MI->addRegOperand(ResultReg, MachineOperand::Def); + MI->addRegOperand(ResultReg, true); for (unsigned i = 1; i != NumResults; ++i) { const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i); assert(RC && "Isn't a register operand!"); - MI->addRegOperand(RegMap->createVirtualRegister(RC), MachineOperand::Def); + MI->addRegOperand(RegMap->createVirtualRegister(RC), true); } return ResultReg; } @@ -291,7 +291,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, // Get/emit the operand. unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, MachineOperand::Use); + MI->addRegOperand(VReg, false); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -307,7 +307,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, MI->addImmOperand(C->getValue()); } else if (RegisterSDNode*R = dyn_cast(Op)) { - MI->addRegOperand(R->getReg(), MachineOperand::Use); + MI->addRegOperand(R->getReg(), false); } else if (GlobalAddressSDNode *TGA = dyn_cast(Op)) { MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset()); @@ -349,7 +349,7 @@ void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op, Op.getValueType() != MVT::Flag && "Chain and flag operands should occur at end of operand list!"); unsigned VReg = getVR(Op, VRBaseMap); - MI->addRegOperand(VReg, MachineOperand::Use); + MI->addRegOperand(VReg, false); // Verify that it is right. assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); @@ -402,7 +402,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned Reg = cast(Use->getOperand(1))->getReg(); if (MRegisterInfo::isVirtualRegister(Reg)) { VRBase = Reg; - MI->addRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, true); break; } } @@ -529,13 +529,13 @@ void ScheduleDAG::EmitNode(SDNode *Node, case 1: // Use of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, MachineOperand::Use); + MI->addRegOperand(Reg, false); } break; case 2: // Def of register. for (; NumVals; --NumVals, ++i) { unsigned Reg = cast(Node->getOperand(i))->getReg(); - MI->addRegOperand(Reg, MachineOperand::Def); + MI->addRegOperand(Reg, true); } break; case 3: { // Immediate. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 317c1e90bf7..b1f70cdf222 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -3547,7 +3547,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, MachineInstr *PHI = PHINodesToUpdate[i].first; assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); - PHI->addRegOperand(PHINodesToUpdate[i].second); + PHI->addRegOperand(PHINodesToUpdate[i].second, false); PHI->addMachineBasicBlockOperand(BB); } return; @@ -3576,11 +3576,11 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); if (PHIBB == JT.Default) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(RangeBB); } if (BB->succ_end() != std::find(BB->succ_begin(),BB->succ_end(), PHIBB)) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(BB); } } @@ -3610,7 +3610,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF, assert(PHI->getOpcode() == TargetInstrInfo::PHI && "This is not a machine PHI node that we are updating!"); if (PHIBB == SwitchCases[i].LHSBB || PHIBB == SwitchCases[i].RHSBB) { - PHI->addRegOperand(PHINodesToUpdate[pi].second); + PHI->addRegOperand(PHINodesToUpdate[pi].second, false); PHI->addMachineBasicBlockOperand(BB); } } diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index c5eef119520..9e6708141ab 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -107,7 +107,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { assert (Offset >= 0); if (Offset < 4096) { // Replace the FrameIndex with r13 - MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13); + MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13, false); // Replace the ldr offset with Offset MI.getOperand(OffIdx).ChangeToImmediate(Offset); } else { @@ -117,7 +117,7 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset); // Replace the FrameIndex with r12 - MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12); + MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false); } } diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 772840a3eb6..1b6fa449083 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -67,14 +67,18 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned SrcReg, int FrameIdx, const TargetRegisterClass *RC) const { - //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; + //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " + //<< FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::STS, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::STS, 3) + .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::STT, 3) + .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::STQ, 3) + .addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); } @@ -84,13 +88,17 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC) const { - //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; + //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " + //<< FrameIdx << "\n"; if (RC == Alpha::F4RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDS, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::LDS, 2, DestReg) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) - BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::LDT, 2, DestReg) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) - BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31); + BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg) + .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); } @@ -243,7 +251,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { int FrameIndex = MI.getOperand(i).getFrameIndex(); // Add the base register of R30 (SP) or R15 (FP). - MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30); + MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30, false); // Now add the frame object offset to the offset from the virtual frame index. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -256,11 +264,12 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { " for stack size: " << MF.getFrameInfo()->getStackSize() << "\n"); if (Offset > IMM_HIGH || Offset < IMM_LOW) { - DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " << Offset << "\n"); - //so in this case, we need to use a temporary register, and move the original - //inst off the SP/FP + DEBUG(std::cerr << "Unconditionally using R28 for evil purposes Offset: " + << Offset << "\n"); + //so in this case, we need to use a temporary register, and move the + //original inst off the SP/FP //fix up the old: - MI.getOperand(i + 1).ChangeToRegister(Alpha::R28); + MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) @@ -335,9 +344,11 @@ void AlphaRegisterInfo::emitPrologue(MachineFunction &MF) const { //now if we need to, save the old FP and set the new if (FP) { - BuildMI(MBB, MBBI, Alpha::STQ, 3).addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); + BuildMI(MBB, MBBI, Alpha::STQ, 3) + .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); //this must be the last instr in the prolog - BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15).addReg(Alpha::R30).addReg(Alpha::R30); + BuildMI(MBB, MBBI, Alpha::BIS, 2, Alpha::R15) + .addReg(Alpha::R30).addReg(Alpha::R30); } } @@ -346,7 +357,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getOpcode() == Alpha::RETDAG || MBBI->getOpcode() == Alpha::RETDAGp + assert(MBBI->getOpcode() == Alpha::RETDAG || + MBBI->getOpcode() == Alpha::RETDAGp && "Can only insert epilog into returning blocks"); bool FP = hasFP(MF); diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp index 7fcd502de9b..ff927503d62 100644 --- a/lib/Target/IA64/IA64RegisterInfo.cpp +++ b/lib/Target/IA64/IA64RegisterInfo.cpp @@ -85,7 +85,8 @@ void IA64RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, if(RC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg).addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); + BuildMI(MBB, MI, IA64::PCMPEQUNC, 3, DestReg) + .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) BuildMI(MBB, MI, IA64::MOV, 1, DestReg).addReg(SrcReg); } @@ -152,7 +153,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MBB.erase(I); } -void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ +void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II)const{ unsigned i = 0; MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); @@ -170,7 +171,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const // choose a base register: ( hasFP? framepointer : stack pointer ) unsigned BaseRegister = FP ? IA64::r5 : IA64::r12; // Add the base register - MI.getOperand(i).ChangeToRegister(BaseRegister); + MI.getOperand(i).ChangeToRegister(BaseRegister, false); // Now add the frame object offset to the offset from r1. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); @@ -181,20 +182,16 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const Offset += MF.getFrameInfo()->getStackSize(); // XXX: we use 'r22' as another hack+slash temporary register here :( - if ( Offset <= 8191 && Offset >= -8192) { // smallish offset - //fix up the old: - MI.getOperand(i).ChangeToRegister(IA64::r22); - MI.getOperand(i).setUse(); // mark r22 as being used - // (the bundler wants to know this) + if (Offset <= 8191 && Offset >= -8192) { // smallish offset + // Fix up the old: + MI.getOperand(i).ChangeToRegister(IA64::r22, false); //insert the new MachineInstr* nMI=BuildMI(IA64::ADDIMM22, 2, IA64::r22) .addReg(BaseRegister).addImm(Offset); MBB.insert(II, nMI); } else { // it's big //fix up the old: - MI.getOperand(i).ChangeToRegister(IA64::r22); - MI.getOperand(i).setUse(); // mark r22 as being used - // (the bundler wants to know this) + MI.getOperand(i).ChangeToRegister(IA64::r22, false); MachineInstr* nMI; nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(Offset); MBB.insert(II, nMI); @@ -242,7 +239,8 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { unsigned numOutRegsUsed=MF.getInfo()->outRegsUsed; - // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ a pseudo_alloc in the MBB) + // XXX FIXME : this code should be a bit more reliable (in case there _isn't_ + // a pseudo_alloc in the MBB) unsigned dstRegOfPseudoAlloc; for(MBBI = MBB.begin(); /*MBBI->getOpcode() != IA64::PSEUDO_ALLOC*/; ++MBBI) { assert(MBBI != MBB.end()); @@ -284,7 +282,7 @@ void IA64RegisterInfo::emitPrologue(MachineFunction &MF) const { // adjust stack pointer: r12 -= numbytes if (NumBytes <= 8191) { - MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes); + MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(-NumBytes); MBB.insert(MBBI, MI); } else { // we use r22 as a scratch register here MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(-NumBytes); @@ -332,7 +330,7 @@ void IA64RegisterInfo::emitEpilogue(MachineFunction &MF, if (NumBytes != 0) { if (NumBytes <= 8191) { - MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes); + MI=BuildMI(IA64::ADDIMM22,2,IA64::r12).addReg(IA64::r12).addImm(NumBytes); MBB.insert(MBBI, MI); } else { MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes); diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index bf50e3579ee..34c23bd1faa 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -421,7 +421,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { int FrameIndex = MI.getOperand(i).getFrameIndex(); // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP). - MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1, false); // Take into account whether it's an add or mem instruction unsigned OffIdx = (i == 2) ? 1 : 2; @@ -466,8 +466,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { "No indexed form of load or store available!"); unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second; MI.setOpcode(NewOpcode); - MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg()); - MI.getOperand(2).ChangeToRegister(PPC::R0); + MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg(), false); + MI.getOperand(2).ChangeToRegister(PPC::R0, false); } else { if (isIXAddr) { assert((Offset & 3) == 0 && "Invalid frame offset!"); diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 7331ebdbff5..81ebdba3f2b 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -147,7 +147,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { if (Offset >= -4096 && Offset <= 4095) { // If the offset is small enough to fit in the immediate field, directly // encode it. - MI.getOperand(i).ChangeToRegister(SP::I6); + MI.getOperand(i).ChangeToRegister(SP::I6, false); MI.getOperand(i+1).ChangeToImmediate(Offset); } else { // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to @@ -158,7 +158,7 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { BuildMI(*MI.getParent(), II, SP::ADDrr, 2, SP::G1).addReg(SP::G1).addReg(SP::I6); // Insert: G1+%lo(offset) into the user. - MI.getOperand(i).ChangeToRegister(SP::G1); + MI.getOperand(i).ChangeToRegister(SP::G1, false); MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1)); } } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 89cc8f2c942..e4c05c6db25 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -168,7 +168,7 @@ static MachineInstr *FuseInst(unsigned Opcode, unsigned OpNo, assert(MO.isReg() && "Expected to fold into reg operand!"); MIB = addFrameReference(MIB, FrameIndex); } else if (MO.isReg()) - MIB = MIB.addReg(MO.getReg(), MO.getUseType()); + MIB = MIB.addReg(MO.getReg(), MO.isDef()); else if (MO.isImm()) MIB = MIB.addImm(MO.getImm()); else if (MO.isGlobalAddress()) @@ -795,7 +795,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{ // This must be part of a four operand memory reference. Replace the // FrameIndex with base register with EBP. Add add an offset to the offset. - MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP); + MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP, false); // Now add the frame object offset to the offset from EBP. int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +