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Add skeleton for the pre-register allocation live interval splitting pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57847 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -61,6 +61,8 @@ namespace llvm {
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/// This pass is still in development
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/// This pass is still in development
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extern const PassInfo *const StrongPHIEliminationID;
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extern const PassInfo *const StrongPHIEliminationID;
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extern const PassInfo *const PreAllocSplittingID;
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/// SimpleRegisterCoalescing pass. Aggressively coalesces every register
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/// SimpleRegisterCoalescing pass. Aggressively coalesces every register
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/// copy it can.
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/// copy it can.
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///
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///
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81
lib/CodeGen/PreAllocSplitting.cpp
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81
lib/CodeGen/PreAllocSplitting.cpp
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@ -0,0 +1,81 @@
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//===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the machine instruction level pre-register allocation
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// live interval splitting pass. It finds live interval barriers, i.e.
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// instructions which will kill all physical registers in certain register
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// classes, and split all live intervals which cross the barrier.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "pre-alloc-split"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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using namespace llvm;
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namespace {
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class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
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// ProcessedBarriers - Register live interval barriers that have already
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// been processed.
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SmallPtrSet<MachineInstr*, 16> ProcessedBarriers;
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// ActiveBarriers - Register live interval barriers that are currently
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// being processed.
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SmallSet<unsigned, 16> ActiveBarriers;
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public:
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static char ID;
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PreAllocSplitting() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<RegisterCoalescer>();
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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AU.addPreservedID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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ProcessedBarriers.clear();
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ActiveBarriers.clear();
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}
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virtual const char *getPassName() const {
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return "Pre-Register Allocaton Live Interval Splitting";
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}
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};
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} // end anonymous namespace
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char PreAllocSplitting::ID = 0;
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static RegisterPass<PreAllocSplitting>
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X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
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const PassInfo *const llvm::PreAllocSplittingID = &X;
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bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
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return false;
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}
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