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SelectionDAGBuilder: style fixes (add space between end parentheses and open brace)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stephen Lin 2013-07-06 21:44:25 +00:00
parent 2a9683289b
commit 09f8ca3986
1 changed files with 10 additions and 10 deletions
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20
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -1476,7 +1476,7 @@ void SelectionDAGBuilder::FindMergedConditions(const Value *Cond,
/// If we should emit this as a bunch of and/or'd together conditions, return
/// false.
bool
SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){
SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases) {
if (Cases.size() != 2) return true;
// If this is two comparisons of the same values or'd or and'd together, they
@ -2039,12 +2039,11 @@ bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR,
// The last case block won't fall through into 'NextBlock' if we emit the
// branches in this order. See if rearranging a case value would help.
// We start at the bottom as it's the case with the least weight.
for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I){
for (Case *I = &*(CR.Range.second-2), *E = &*CR.Range.first-1; I != E; --I)
if (I->BB == NextBlock) {
std::swap(*I, BackCase);
break;
}
}
}
// Create a CaseBlock record representing a conditional branch to
@ -2227,8 +2226,8 @@ bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR,
bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
const Value* SV,
MachineBasicBlock *Default,
MachineBasicBlock *SwitchBB) {
MachineBasicBlock* Default,
MachineBasicBlock* SwitchBB) {
// Get the MachineFunction which holds the current MBB. This is used when
// inserting any additional MBBs necessary to represent the switch.
MachineFunction *CurMF = FuncInfo.MF;
@ -2363,7 +2362,7 @@ bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR,
CaseRecVector& WorkList,
const Value* SV,
MachineBasicBlock* Default,
MachineBasicBlock *SwitchBB){
MachineBasicBlock* SwitchBB) {
const TargetLowering *TLI = TM.getTargetLowering();
EVT PTy = TLI->getPointerTy();
unsigned IntPtrBits = PTy.getSizeInBits();
@ -2793,7 +2792,7 @@ void SelectionDAGBuilder::visitFPTrunc(const User &I) {
DAG.getTargetConstant(0, TLI->getPointerTy())));
}
void SelectionDAGBuilder::visitFPExt(const User &I){
void SelectionDAGBuilder::visitFPExt(const User &I) {
// FPExt is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
@ -2821,7 +2820,7 @@ void SelectionDAGBuilder::visitUIToFP(const User &I) {
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurSDLoc(), DestVT, N));
}
void SelectionDAGBuilder::visitSIToFP(const User &I){
void SelectionDAGBuilder::visitSIToFP(const User &I) {
// SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
EVT DestVT = TM.getTargetLowering()->getValueType(I.getType());
@ -4354,7 +4353,8 @@ static unsigned getTruncatedArgReg(const SDValue &N) {
return 0;
const SDValue &Ext = N.getOperand(0);
if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){
if (Ext.getOpcode() == ISD::AssertZext ||
Ext.getOpcode() == ISD::AssertSext) {
const SDValue &CFR = Ext.getOperand(0);
if (CFR.getOpcode() == ISD::CopyFromReg)
return cast<RegisterSDNode>(CFR.getOperand(1))->getReg();
@ -4922,7 +4922,7 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
case Intrinsic::fmuladd: {
EVT VT = TLI->getValueType(I.getType());
if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
TLI->isFMAFasterThanMulAndAdd(VT)){
TLI->isFMAFasterThanMulAndAdd(VT)) {
setValue(&I, DAG.getNode(ISD::FMA, sdl,
getValue(I.getArgOperand(0)).getValueType(),
getValue(I.getArgOperand(0)),