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TypeLegalizer: Do not generate target specific nodes with illegal types, because we cant type-legalize them.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170245 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem 2012-12-14 21:20:37 +00:00
parent 58d15b5b21
commit 0a1e914f8f
2 changed files with 25 additions and 0 deletions
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3
lib/Target/X86/X86ISelLowering.cpp
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@ -11742,6 +11742,7 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
SmallVectorImpl<SDValue>&Results,
SelectionDAG &DAG) const {
DebugLoc dl = N->getDebugLoc();
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
switch (N->getOpcode()) {
default:
llvm_unreachable("Do not know how to custom type legalize this operation!");
@ -11791,6 +11792,8 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
return;
}
case ISD::FP_ROUND: {
if (!TLI.isTypeLegal(N->getOperand(0).getValueType()))
return;
SDValue V = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, N->getOperand(0));
Results.push_back(V);
return;

22
test/CodeGen/X86/2012-12-14-v8fp80-crash.ll Normal file
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@ -0,0 +1,22 @@
; RUN: llc < %s -march=x86 -mcpu=corei7 -mtriple=i686-pc-win32
; Make sure we don't crash on this testcase.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-macosx10.9.0"
define void @_ZN6VectorIfE3equIeEEvfRKS_IT_E() nounwind uwtable ssp align 2 {
entry:
br i1 undef, label %while.end, label %while.body.lr.ph
while.body.lr.ph: ; preds = %entry
br label %vector.body
vector.body: ; preds = %vector.body, %while.body.lr.ph
%0 = fptrunc <8 x x86_fp80> undef to <8 x float>
store <8 x float> %0, <8 x float>* undef, align 4
br label %vector.body
while.end: ; preds = %entry
ret void
}