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Add intel style operand parser skeleton.
This is a work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148002 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -46,6 +46,8 @@ private:
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}
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X86Operand *ParseOperand();
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X86Operand *ParseATTOperand();
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X86Operand *ParseIntelOperand();
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X86Operand *ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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@ -495,6 +497,99 @@ bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
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}
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X86Operand *X86ATTAsmParser::ParseOperand() {
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if (getParser().getAssemblerDialect())
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return ParseIntelOperand();
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return ParseATTOperand();
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}
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/// getIntelRegister - If this is an intel register operand
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/// then return register number, otherwise return 0;
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static unsigned getIntelRegisterOperand(StringRef Str) {
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unsigned RegNo = MatchRegisterName(Str);
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// If the match failed, try the register name as lowercase.
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if (RegNo == 0)
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RegNo = MatchRegisterName(Str.lower());
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return RegNo;
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}
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/// isIntelMemOperand - If this is an intel memory operand
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/// then return true.
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static bool isIntelMemOperand(StringRef OpStr, unsigned &Size) {
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Size = 0;
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if (OpStr == "BYTE") Size = 8;
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if (OpStr == "WORD") Size = 16;
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if (OpStr == "DWORD") Size = 32;
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if (OpStr == "QWORD") Size = 64;
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if (OpStr == "XWORD") Size = 80;
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if (OpStr == "XMMWORD") Size = 128;
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if (OpStr == "YMMWORD") Size = 256;
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return Size != 0;
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}
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X86Operand *X86ATTAsmParser::ParseIntelOperand() {
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const AsmToken &Tok = Parser.getTok();
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SMLoc Start = Parser.getTok().getLoc(), End;
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// register
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if(unsigned RegNo = getIntelRegisterOperand(Tok.getString())) {
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Parser.Lex();
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End = Parser.getTok().getLoc();
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return X86Operand::CreateReg(RegNo, Start, End);
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}
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// mem operand
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unsigned SegReg = 0, BaseReg = 0, IndexReg = 0, Scale = 1;
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StringRef OpStr = Tok.getString();
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unsigned Size = 0;
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if (isIntelMemOperand(OpStr, Size)) {
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Parser.Lex();
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if (Tok.getString() == "PTR")
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Parser.Lex();
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else {
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Error(Start, "unexpected token!");
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return 0;
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}
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if (Tok.getString() == "[")
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Parser.Lex();
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else {
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Error(Start, "unexpected token!");
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return 0;
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}
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SMLoc LParenLoc = Parser.getTok().getLoc();
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BaseReg = getIntelRegisterOperand(Tok.getString());
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if (BaseReg == 0) {
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Error(LParenLoc, "unexpected token!");
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return 0;
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}
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Parser.Lex();
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const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
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SMLoc ExprEnd;
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if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
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End = Parser.getTok().getLoc();
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if (Tok.getString() == "]")
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Parser.Lex();
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if (BaseReg == 0) {
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Error(End, "unexpected token!");
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return 0;
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}
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return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
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Start, End);
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}
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// immediate.
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const MCExpr *Val;
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if (!getParser().ParseExpression(Val, End)) {
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End = Parser.getTok().getLoc();
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return X86Operand::CreateImm(Val, Start, End);
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}
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return 0;
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}
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X86Operand *X86ATTAsmParser::ParseATTOperand() {
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switch (getLexer().getKind()) {
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default:
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// Parse a memory operand with no segment register.
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@ -990,7 +1085,8 @@ MatchAndEmitInstruction(SMLoc IDLoc,
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MCInst Inst;
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// First, try a direct match.
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switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
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switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo,
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getParser().getAssemblerDialect())) {
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default: break;
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case Match_Success:
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Out.EmitInstruction(Inst);
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