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Spelling fix: extened->extended. Trailing whitespace in same function.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172793 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-01-18 06:50:59 +00:00
parent 5a529e4f86
commit 0a38861364
1 changed files with 6 additions and 5 deletions
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11
lib/Target/X86/X86ISelLowering.cpp
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@ -16967,29 +16967,30 @@ static SDValue PerformSExtCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget *Subtarget) {
EVT VT = N->getValueType(0);
if (!VT.isVector())
return SDValue();
SDValue In = N->getOperand(0);
EVT InVT = In.getValueType();
DebugLoc dl = N->getDebugLoc();
unsigned ExtenedEltSize = VT.getVectorElementType().getSizeInBits();
unsigned ExtendedEltSize = VT.getVectorElementType().getSizeInBits();
// Split SIGN_EXTEND operation to use vmovsx instruction when possible
if (InVT == MVT::v8i8) {
if (ExtenedEltSize > 16 && !Subtarget->hasInt256())
if (ExtendedEltSize > 16 && !Subtarget->hasInt256())
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, In);
if (ExtenedEltSize > 32)
if (ExtendedEltSize > 32)
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
if ((InVT == MVT::v4i8 || InVT == MVT::v4i16) &&
ExtenedEltSize > 32 && !Subtarget->hasInt256()) {
ExtendedEltSize > 32 && !Subtarget->hasInt256()) {
In = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, In);
return DAG.getNode(ISD::SIGN_EXTEND, dl, VT, In);
}
if (!DCI.isBeforeLegalizeOps())
return SDValue();