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https://github.com/c64scene-ar/llvm-6502.git
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Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58626 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
58d43d4a41
commit
0a4b9dc9b1
@ -82,8 +82,8 @@ namespace {
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const TargetInstrDesc &TID,
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const MachineOperand &MO);
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unsigned getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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unsigned getAddrModeSBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const;
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unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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@ -97,6 +97,9 @@ namespace {
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unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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unsigned getAddrMode6InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary);
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/// getInstrBinary - Return binary encoding for the specified
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/// machine instruction.
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@ -432,8 +435,8 @@ unsigned ARMCodeEmitter::getMachineSoImmOpValue(const MachineInstr &MI,
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return Binary;
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}
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unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const {
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unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
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const TargetInstrDesc &TID) const {
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for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
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const MachineOperand &MO = MI.getOperand(i-1);
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if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
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@ -449,7 +452,7 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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Binary |= II->getPredicate(&MI) << 28;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrMode1SBit(MI, TID);
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Binary |= getAddrModeSBit(MI, TID);
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// Encode register def if there is one.
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unsigned NumDefs = TID.getNumDefs();
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@ -618,6 +621,33 @@ unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
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return Binary;
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}
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unsigned ARMCodeEmitter::getAddrMode6InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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// Set the conditional execution predicate
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Binary |= II->getPredicate(&MI) << 28;
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// Encode S bit if MI modifies CPSR.
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Binary |= getAddrModeSBit(MI, TID);
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// 32x32->64bit operations have two destination registers. The number
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// of register definitions will tell us if that's what we're dealing with.
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int OpIdx = 0;
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if (TID.getNumDefs() == 2)
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Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
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// Encode Rd
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
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// Encode Rm
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Binary |= getMachineOpValue(MI, OpIdx++);
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// Encode Rs
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Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
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return Binary;
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}
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/// getInstrBinary - Return binary encoding for the specified
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/// machine instruction.
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unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
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@ -636,6 +666,8 @@ unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
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return getAddrMode3InstrBinary(MI, TID, Binary);
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case ARMII::AddrMode4:
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return getAddrMode4InstrBinary(MI, TID, Binary);
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case ARMII::AddrMode6:
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return getAddrMode6InstrBinary(MI, TID, Binary);
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}
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abort();
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@ -659,6 +659,28 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
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let Inst{27-25} = 0b100;
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}
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// addrmode6
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// Unsigned multiply, multiply-accumulate instructions.
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class AI6<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: I<opcod, oops, iops, AddrMode6, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>
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{
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// FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
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let Inst{7-4} = 0b1001;
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let Inst{27-24} = 0b0000;
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let Inst{23-20} = opcod;
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}
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class AsI6<bits<4> opcod, dag oops, dag iops, Format f, string opc,
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string asm, list<dag> pattern>
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: sI<opcod, oops, iops, AddrMode6, Size4Bytes, IndexModeNone, f, opc,
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asm,"",pattern>
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{
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// FIXME: bits 7-4 should be a sub-mode (for SMLAxx, SMLAWy, ...)
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let Inst{7-4} = 0b1001;
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let Inst{27-24} = 0b0000;
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let Inst{23-20} = opcod;
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}
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//===----------------------------------------------------------------------===//
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@ -30,8 +30,7 @@ namespace ARMII {
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// Instruction Flags.
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//===------------------------------------------------------------------===//
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// This three-bit field describes the addressing mode used. Zero is unused
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// so that we can tell if we forgot to set a value.
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// This four-bit field describes the addressing mode used.
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AddrModeMask = 0xf,
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AddrModeNone = 0,
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@ -40,10 +39,11 @@ namespace ARMII {
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AddrMode3 = 3,
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AddrMode4 = 4,
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AddrMode5 = 5,
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AddrModeT1 = 6,
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AddrModeT2 = 7,
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AddrModeT4 = 8,
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AddrModeTs = 9, // i8 * 4 for pc and sp relative data
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AddrMode6 = 6,
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AddrModeT1 = 7,
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AddrModeT2 = 8,
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AddrModeT4 = 9,
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AddrModeTs = 10, // i8 * 4 for pc and sp relative data
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// Size* - Flags to keep track of the size of an instruction.
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SizeShift = 4,
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@ -115,15 +115,17 @@ namespace ARMII {
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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RotImmShift = 8,
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RegRsShift = 8,
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RegRdShift = 12,
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RegRnShift = 16,
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L_BitShift = 20,
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S_BitShift = 20,
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U_BitShift = 23,
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IndexShift = 24,
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I_BitShift = 25
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RotImmShift = 8,
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RegRsShift = 8,
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RegRdLoShift = 12,
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RegRdShift = 12,
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RegRdHiShift = 16,
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RegRnShift = 16,
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L_BitShift = 20,
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S_BitShift = 20,
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U_BitShift = 23,
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IndexShift = 24,
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I_BitShift = 25
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};
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}
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@ -310,10 +310,11 @@ def AddrMode2 : AddrMode<2>;
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def AddrMode3 : AddrMode<3>;
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def AddrMode4 : AddrMode<4>;
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def AddrMode5 : AddrMode<5>;
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def AddrModeT1 : AddrMode<6>;
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def AddrModeT2 : AddrMode<7>;
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def AddrModeT4 : AddrMode<8>;
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def AddrModeTs : AddrMode<9>;
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def AddrMode6 : AddrMode<6>;
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def AddrModeT1 : AddrMode<7>;
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def AddrModeT2 : AddrMode<8>;
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def AddrModeT4 : AddrMode<9>;
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def AddrModeTs : AddrMode<10>;
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// Instruction size.
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class SizeFlagVal<bits<3> val> {
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@ -910,49 +911,53 @@ def : ARMPat<(and GPR:$src, so_imm_not:$imm),
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// Multiply Instructions.
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//
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def MUL : AsI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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"mul", " $dst, $a, $b",
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[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
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def MUL : AsI6<0b0000, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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"mul", " $dst, $a, $b",
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[(set GPR:$dst, (mul GPR:$a, GPR:$b))]>;
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def MLA : AsI<0x2, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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MulFrm, "mla", " $dst, $a, $b, $c",
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[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
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def MLA : AsI6<0b0010, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
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MulFrm, "mla", " $dst, $a, $b, $c",
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[(set GPR:$dst, (add (mul GPR:$a, GPR:$b), GPR:$c))]>;
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// Extra precision multiplies with low / high results
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def SMULL : AsI<0xC, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
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def SMULL : AsI6<0b1100, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "smull", " $ldst, $hdst, $a, $b", []>;
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def UMULL : AsI<0x8, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
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def UMULL : AsI6<0b1000, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "umull", " $ldst, $hdst, $a, $b", []>;
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// Multiply + accumulate
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def SMLAL : AsI<0xE, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
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def SMLAL : AsI6<0b1110, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "smlal", " $ldst, $hdst, $a, $b", []>;
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def UMLAL : AsI<0xA, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
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def UMLAL : AsI6<0b1010, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "umlal", " $ldst, $hdst, $a, $b", []>;
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def UMAAL : AI<0x0, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b), MulFrm,
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"umaal", " $ldst, $hdst, $a, $b", []>,
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Requires<[IsARM, HasV6]>;
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def UMAAL : AI6 <0b0000, (outs GPR:$ldst, GPR:$hdst), (ins GPR:$a, GPR:$b),
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MulFrm, "umaal", " $ldst, $hdst, $a, $b", []>,
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Requires<[IsARM, HasV6]>;
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// Most significant word multiply
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// FIXME: encoding
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def SMMUL : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulFrm,
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"smmul", " $dst, $a, $b",
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[(set GPR:$dst, (mulhs GPR:$a, GPR:$b))]>,
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Requires<[IsARM, HasV6]>;
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// FIXME: encoding
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def SMMLA : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
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"smmla", " $dst, $a, $b, $c",
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[(set GPR:$dst, (add (mulhs GPR:$a, GPR:$b), GPR:$c))]>,
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Requires<[IsARM, HasV6]>;
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// FIXME: encoding
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def SMMLS : AI<0x0, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c), MulFrm,
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"smmls", " $dst, $a, $b, $c",
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[(set GPR:$dst, (sub GPR:$c, (mulhs GPR:$a, GPR:$b)))]>,
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Requires<[IsARM, HasV6]>;
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// FIXME: encoding
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multiclass AI_smul<string opc, PatFrag opnode> {
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def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b), MulSMUL,
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!strconcat(opc, "bb"), " $dst, $a, $b",
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@ -992,6 +997,7 @@ multiclass AI_smul<string opc, PatFrag opnode> {
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}
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// FIXME: encoding
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multiclass AI_smla<string opc, PatFrag opnode> {
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def BB : AI<0x8, (outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$acc), MulSMLA,
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!strconcat(opc, "bb"), " $dst, $a, $b, $acc",
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@ -1031,7 +1037,9 @@ multiclass AI_smla<string opc, PatFrag opnode> {
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Requires<[IsARM, HasV5TE]>;
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}
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// FIXME: encoding
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defm SMUL : AI_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// FIXME: encoding
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defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
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// TODO: Halfword multiple accumulate long: SMLAL<x><y>
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