From 0a57dc1d147bbd091adf89ace10482ceb912c552 Mon Sep 17 00:00:00 2001 From: Akira Hatanaka Date: Fri, 21 Dec 2012 23:01:24 +0000 Subject: [PATCH] [mips] Refactor load/store left/right and load-link and store-conditional instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170950 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Mips/Mips64InstrInfo.td | 33 +++++----- lib/Target/Mips/MipsInstrInfo.td | 96 +++++++++++------------------- 2 files changed, 51 insertions(+), 78 deletions(-) diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index 17455b75b6d..42eebc764f1 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -142,28 +142,25 @@ defm SD : StoreM<"sd", store, CPU64Regs>, LW_FM<0x3f>; /// load/store left/right let isCodeGenOnly = 1 in { - defm LWL64 : LoadLeftRightM64<0x22, "lwl", MipsLWL>; - defm LWR64 : LoadLeftRightM64<0x26, "lwr", MipsLWR>; - defm SWL64 : StoreLeftRightM64<0x2a, "swl", MipsSWL>; - defm SWR64 : StoreLeftRightM64<0x2e, "swr", MipsSWR>; + defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>; + defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>; + defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>; + defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>; } -defm LDL : LoadLeftRightM64<0x1a, "ldl", MipsLDL>; -defm LDR : LoadLeftRightM64<0x1b, "ldr", MipsLDR>; -defm SDL : StoreLeftRightM64<0x2c, "sdl", MipsSDL>; -defm SDR : StoreLeftRightM64<0x2d, "sdr", MipsSDR>; +defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>; +defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>; +defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>; +defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>; /// Load-linked, Store-conditional -def LLD : LLBase<0x34, "lld", CPU64Regs, mem>, - Requires<[NotN64, HasStdEnc]>; -def LLD_P8 : LLBase<0x34, "lld", CPU64Regs, mem64>, - Requires<[IsN64, HasStdEnc]> { - let isCodeGenOnly = 1; +let Predicates = [NotN64, HasStdEnc] in { + def LLD : LLBase<"lld", CPU64Regs, mem>, LW_FM<0x34>; + def SCD : SCBase<"scd", CPU64Regs, mem>, LW_FM<0x3c>; } -def SCD : SCBase<0x3c, "scd", CPU64Regs, mem>, - Requires<[NotN64, HasStdEnc]>; -def SCD_P8 : SCBase<0x3c, "scd", CPU64Regs, mem64>, - Requires<[IsN64, HasStdEnc]> { - let isCodeGenOnly = 1; + +let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in { + def LLD_P8 : LLBase<"lld", CPU64Regs, mem64>, LW_FM<0x34>; + def SCD_P8 : SCBase<"scd", CPU64Regs, mem64>, LW_FM<0x3c>; } /// Jump and Branch Instructions diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 55c87218ce8..37c710b34ec 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -435,58 +435,36 @@ multiclass StoreM { // Load/Store Left/Right let canFoldAsLoad = 1 in -class LoadLeftRight op, string instr_asm, SDNode OpNode, - RegisterClass RC, Operand MemOpnd> : - FMem { +class LoadLeftRight : + InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), + !strconcat(opstr, "\t$rt, $addr"), + [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; string Constraints = "$src = $rt"; } -class StoreLeftRight op, string instr_asm, SDNode OpNode, - RegisterClass RC, Operand MemOpnd>: - FMem; +class StoreLeftRight: + InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), + [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; +} -// 32-bit load left/right. -multiclass LoadLeftRightM32 op, string instr_asm, SDNode OpNode> { - def #NAME# : LoadLeftRight, +multiclass LoadLeftRightM { + def #NAME# : LoadLeftRight, Requires<[NotN64, HasStdEnc]>; - def _P8 : LoadLeftRight, + def _P8 : LoadLeftRight, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; } } -// 64-bit load left/right. -multiclass LoadLeftRightM64 op, string instr_asm, SDNode OpNode> { - def #NAME# : LoadLeftRight, +multiclass StoreLeftRightM { + def #NAME# : StoreLeftRight, Requires<[NotN64, HasStdEnc]>; - def _P8 : LoadLeftRight, - Requires<[IsN64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } -} - -// 32-bit store left/right. -multiclass StoreLeftRightM32 op, string instr_asm, SDNode OpNode> { - def #NAME# : StoreLeftRight, - Requires<[NotN64, HasStdEnc]>; - def _P8 : StoreLeftRight, - Requires<[IsN64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; - let isCodeGenOnly = 1; - } -} - -// 64-bit store left/right. -multiclass StoreLeftRightM64 op, string instr_asm, SDNode OpNode> { - def #NAME# : StoreLeftRight, - Requires<[NotN64, HasStdEnc]>; - def _P8 : StoreLeftRight, + def _P8 : StoreLeftRight, Requires<[IsN64, HasStdEnc]> { let DecoderNamespace = "Mips64"; let isCodeGenOnly = 1; @@ -736,15 +714,17 @@ multiclass AtomicCmpSwap32 { } } -class LLBase Opc, string opstring, RegisterClass RC, Operand Mem> : - FMem { +class LLBase : + InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), + [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; let mayLoad = 1; } -class SCBase Opc, string opstring, RegisterClass RC, Operand Mem> : - FMem { +class SCBase : + InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + let DecoderMethod = "DecodeMem"; let mayStore = 1; let Constraints = "$rt = $dst"; } @@ -850,10 +830,10 @@ defm SH : StoreM<"sh", truncstorei16, CPURegs>, LW_FM<0x29>; defm SW : StoreM<"sw", store, CPURegs>, LW_FM<0x2b>; /// load/store left/right -defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; -defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; -defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; -defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; +defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; +defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; +defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; +defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; let hasSideEffects = 1 in def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", @@ -867,18 +847,14 @@ def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", } /// Load-linked, Store-conditional -def LL : LLBase<0x30, "ll", CPURegs, mem>, - Requires<[NotN64, HasStdEnc]>; -def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, - Requires<[IsN64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; +let Predicates = [NotN64, HasStdEnc] in { + def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>; + def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>; } -def SC : SCBase<0x38, "sc", CPURegs, mem>, - Requires<[NotN64, HasStdEnc]>; -def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, - Requires<[IsN64, HasStdEnc]> { - let DecoderNamespace = "Mips64"; +let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { + def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>; + def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>; } /// Jump and Branch Instructions