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Merge still more SSE/AVX instruction definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2681,12 +2681,12 @@ multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
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ValueType OpVT128, ValueType OpVT256,
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ValueType OpVT128, ValueType OpVT256,
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OpndItins itins, bit IsCommutable = 0> {
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OpndItins itins, bit IsCommutable = 0> {
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let Predicates = [HasAVX] in
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let Predicates = [HasAVX] in
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defm VP#NAME# : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
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defm VP#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
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VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
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VR128, memopv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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let Constraints = "$src1 = $dst" in
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defm P#NAME# : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
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defm P#NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
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memopv2i64, i128mem, itins, IsCommutable, 1>;
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memopv2i64, i128mem, itins, IsCommutable, 1>;
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let Predicates = [HasAVX2] in
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let Predicates = [HasAVX2] in
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
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defm VP#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
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@ -3632,13 +3632,13 @@ multiclass PDI_binop_all_int<bits<8> opc, string OpcodeStr, Intrinsic IntId128,
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Intrinsic IntId256, OpndItins itins,
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Intrinsic IntId256, OpndItins itins,
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bit IsCommutable = 0> {
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bit IsCommutable = 0> {
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let Predicates = [HasAVX] in
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let Predicates = [HasAVX] in
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defm VP#NAME# : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
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defm VP#NAME : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId128,
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VR128, memopv2i64, i128mem, itins,
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VR128, memopv2i64, i128mem, itins,
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IsCommutable, 0>, VEX_4V;
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IsCommutable, 0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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let Constraints = "$src1 = $dst" in
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defm P#NAME# : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
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defm P#NAME : PDI_binop_rm_int<opc, OpcodeStr, IntId128, VR128, memopv2i64,
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i128mem, itins, IsCommutable, 1>;
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i128mem, itins, IsCommutable, 1>;
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let Predicates = [HasAVX2] in
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let Predicates = [HasAVX2] in
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defm VP#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
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defm VP#NAME#Y : PDI_binop_rm_int<opc, !strconcat("v", OpcodeStr), IntId256,
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@ -3965,41 +3965,13 @@ defm CMPGTD : PDI_binop_all<0x66, "pcmpgtd", X86pcmpgt, v4i32, v8i32,
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// SSE2 - Packed Integer Pack Instructions
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// SSE2 - Packed Integer Pack Instructions
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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let Predicates = [HasAVX] in {
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// FIXME: Names are bad due to the need to have a 'P' prefix in the multiclass.
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defm VPACKSSWB : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_sse2_packsswb_128,
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defm ACKSSWB : PDI_binop_all_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
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VR128, memopv2i64, i128mem,
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int_x86_avx2_packsswb, SSE_INTALU_ITINS_P, 0>;
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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defm ACKSSDW : PDI_binop_all_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
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defm VPACKSSDW : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_sse2_packssdw_128,
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int_x86_avx2_packssdw, SSE_INTALU_ITINS_P, 0>;
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VR128, memopv2i64, i128mem,
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defm ACKUSWB : PDI_binop_all_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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int_x86_avx2_packuswb, SSE_INTALU_ITINS_P, 0>;
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defm VPACKUSWB : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_sse2_packuswb_128,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V;
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}
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let Predicates = [HasAVX2] in {
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defm VPACKSSWBY : PDI_binop_rm_int<0x63, "vpacksswb", int_x86_avx2_packsswb,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPACKSSDWY : PDI_binop_rm_int<0x6B, "vpackssdw", int_x86_avx2_packssdw,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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defm VPACKUSWBY : PDI_binop_rm_int<0x67, "vpackuswb", int_x86_avx2_packuswb,
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VR256, memopv4i64, i256mem,
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SSE_INTALU_ITINS_P, 0, 0>, VEX_4V, VEX_L;
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}
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let Constraints = "$src1 = $dst" in {
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defm PACKSSWB : PDI_binop_rm_int<0x63, "packsswb", int_x86_sse2_packsswb_128,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P>;
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defm PACKSSDW : PDI_binop_rm_int<0x6B, "packssdw", int_x86_sse2_packssdw_128,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P>;
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defm PACKUSWB : PDI_binop_rm_int<0x67, "packuswb", int_x86_sse2_packuswb_128,
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VR128, memopv2i64, i128mem,
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SSE_INTALU_ITINS_P>;
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} // Constraints = "$src1 = $dst"
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//===---------------------------------------------------------------------===//
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Shuffle Instructions
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// SSE2 - Packed Integer Shuffle Instructions
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