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Fold ARM coprocessor intrinsics patterns into the instructions defs whenever
it's possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
54ad87ab78
commit
0a69ba309f
@ -3398,7 +3398,8 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
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def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]> {
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bits<4> opc1;
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bits<4> CRn;
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bits<4> CRd;
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@ -3415,14 +3416,11 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{23-20} = opc1;
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}
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def : ARMPat<(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(CDP imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,imm:$opc2)>;
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def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]> {
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let Inst{31-28} = 0b1111;
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bits<4> opc1;
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bits<4> CRn;
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@ -3440,11 +3438,6 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{23-20} = opc1;
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}
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def : ARMPat<(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(CDP2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,
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imm:$opc2)>;
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class ACI<dag oops, dag iops, string opc, string asm,
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IndexMode im = IndexModeNone>
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: InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
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@ -3551,10 +3544,10 @@ defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
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// Move between coprocessor and ARM core register -- for disassembly only
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//
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class MovRCopro<string opc, bit direction, dag oops, dag iops>
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class MovRCopro<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: ABI<0b1110, oops, iops, NoItinerary, opc,
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"\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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"\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
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let Inst{20} = direction;
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let Inst{4} = 1;
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@ -3574,23 +3567,23 @@ class MovRCopro<string opc, bit direction, dag oops, dag iops>
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}
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def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
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(outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2)>;
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(outs),
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(ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2),
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[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
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c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>;
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2), []>;
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def : ARMPat<(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(MCR imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)>;
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def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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(MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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class MovRCopro2<string opc, bit direction, dag oops, dag iops>
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class MovRCopro2<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: ABXI<0b1110, oops, iops, NoItinerary,
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!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
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[/* For disassembly only; pattern left blank */]> {
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!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
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let Inst{31-28} = 0b1111;
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let Inst{20} = direction;
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let Inst{4} = 1;
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@ -3611,27 +3604,25 @@ class MovRCopro2<string opc, bit direction, dag oops, dag iops>
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}
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def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
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(outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2)>;
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(outs),
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(ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2),
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[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1,
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c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2)>;
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
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i32imm:$opc2), []>;
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def : ARMV5TPat<(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(MCR2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)>;
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def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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class MovRRCopro<string opc, bit direction>
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class MovRRCopro<string opc, bit direction,
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list<dag> pattern = [/* For disassembly only */]>
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: ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm",
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[/* For disassembly only; pattern left blank */]> {
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NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -3648,18 +3639,16 @@ class MovRRCopro<string opc, bit direction>
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let Inst{3-0} = CRm;
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}
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def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
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def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
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imm:$CRm)]>;
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def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
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def : ARMV5TEPat<(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
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imm:$CRm),
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(MCRR imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
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class MovRRCopro2<string opc, bit direction>
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class MovRRCopro2<string opc, bit direction,
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list<dag> pattern = [/* For disassembly only */]>
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: ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
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[/* For disassembly only; pattern left blank */]> {
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GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
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let Inst{31-28} = 0b1111;
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -3677,12 +3666,11 @@ class MovRRCopro2<string opc, bit direction>
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let Inst{3-0} = CRm;
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}
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def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>;
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def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
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imm:$CRm)]>;
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def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
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def : ARMV6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
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(MCRR2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
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//===----------------------------------------------------------------------===//
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// Move between special register and ARM core register -- for disassembly only
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//
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@ -1352,9 +1352,10 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
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// Move between coprocessor and ARM core register -- for disassembly only
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//
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class tMovRCopro<string opc, bit direction, dag oops, dag iops>
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class tMovRCopro<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
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[/* For disassembly only; pattern left blank */]> {
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pattern> {
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let Inst{27-24} = 0b1110;
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let Inst{20} = direction;
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let Inst{4} = 1;
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@ -1375,24 +1376,24 @@ class tMovRCopro<string opc, bit direction, dag oops, dag iops>
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}
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def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
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(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2)>;
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(outs),
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(ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2),
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[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2)>;
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(outs GPR:$Rt),
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(ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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[]>;
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def : Pat<(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(tMCR imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)>, Requires<[IsThumb, HasV6T2]>;
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def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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(tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
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Requires<[IsThumb, HasV6T2]>;
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class tMovRRCopro<string opc, bit direction>
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class tMovRRCopro<string opc, bit direction,
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list<dag> pattern = [/* For disassembly only */]>
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: T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
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[/* For disassembly only; pattern left blank */]> {
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
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let Inst{27-24} = 0b1100;
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -1410,20 +1411,19 @@ class tMovRRCopro<string opc, bit direction>
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let Inst{3-0} = CRm;
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}
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def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
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def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
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imm:$CRm)]>;
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def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
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def : Pat<(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
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(tMCRR imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>,
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Requires<[IsThumb, HasV6T2]>;
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//===----------------------------------------------------------------------===//
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// Other Coprocessor Instructions. For disassembly only.
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//
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def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
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c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
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"cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
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[/* For disassembly only; pattern left blank */]> {
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[(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)]> {
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let Inst{27-24} = 0b1110;
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bits<4> opc1;
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@ -1442,11 +1442,6 @@ def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
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let Inst{23-20} = opc1;
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}
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def : Pat<(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(tCDP imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
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imm:$CRm, imm:$opc2)>, Requires<[IsThumb, HasV6T2]>;
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//===----------------------------------------------------------------------===//
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// TLS Instructions
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//
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@ -3347,9 +3347,10 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
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// Move between coprocessor and ARM core register -- for disassembly only
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//
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class t2MovRCopro<string opc, bit direction, dag oops, dag iops>
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class t2MovRCopro<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
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[/* For disassembly only; pattern left blank */]> {
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pattern> {
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let Inst{27-24} = 0b1110;
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let Inst{20} = direction;
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let Inst{4} = 1;
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@ -3371,23 +3372,21 @@ class t2MovRCopro<string opc, bit direction, dag oops, dag iops>
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def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
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(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2)>;
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c_imm:$CRm, i32imm:$opc2),
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[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)]>;
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def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
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c_imm:$CRm, i32imm:$opc2)>;
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c_imm:$CRm, i32imm:$opc2), []>;
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def : T2v6Pat<(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(t2MCR2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
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imm:$CRm, imm:$opc2)>;
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def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
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imm:$CRm, imm:$opc2),
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(t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
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class t2MovRRCopro<string opc, bit direction>
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class t2MovRRCopro<string opc, bit direction,
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list<dag> pattern = [/* For disassembly only */]>
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: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
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[/* For disassembly only; pattern left blank */]> {
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!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
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let Inst{27-24} = 0b1100;
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let Inst{23-21} = 0b010;
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let Inst{20} = direction;
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@ -3406,13 +3405,12 @@ class t2MovRRCopro<string opc, bit direction>
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}
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def t2MCRR2 : t2MovRRCopro<"mcrr2",
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0 /* from ARM core register to coprocessor */>;
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0 /* from ARM core register to coprocessor */,
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[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
|
||||
GPR:$Rt2, imm:$CRm)]>;
|
||||
def t2MRRC2 : t2MovRRCopro<"mrrc2",
|
||||
1 /* from coprocessor to ARM core register */>;
|
||||
|
||||
def : T2v6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
|
||||
(t2MCRR2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Other Coprocessor Instructions. For disassembly only.
|
||||
//
|
||||
@ -3420,7 +3418,8 @@ def : T2v6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
|
||||
def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
|
||||
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
|
||||
"cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
|
||||
[/* For disassembly only; pattern left blank */]> {
|
||||
[(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
|
||||
imm:$CRm, imm:$opc2)]> {
|
||||
let Inst{27-24} = 0b1110;
|
||||
|
||||
bits<4> opc1;
|
||||
@ -3438,8 +3437,3 @@ def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
|
||||
let Inst{19-16} = CRn;
|
||||
let Inst{23-20} = opc1;
|
||||
}
|
||||
|
||||
def : T2v6Pat<(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
|
||||
imm:$CRm, imm:$opc2),
|
||||
(t2CDP2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
|
||||
imm:$CRm, imm:$opc2)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user