Fold ARM coprocessor intrinsics patterns into the instructions defs whenever

it's possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130764 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2011-05-03 17:29:29 +00:00
parent 54ad87ab78
commit 0a69ba309f
3 changed files with 73 additions and 96 deletions

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@ -3398,7 +3398,8 @@ def SWPB : AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, GPR:$Rn), "swpb",
def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> { [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
bits<4> opc1; bits<4> opc1;
bits<4> CRn; bits<4> CRn;
bits<4> CRd; bits<4> CRd;
@ -3415,14 +3416,11 @@ def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
let Inst{23-20} = opc1; let Inst{23-20} = opc1;
} }
def : ARMPat<(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2),
(CDP imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,imm:$opc2)>;
def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> { [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
bits<4> opc1; bits<4> opc1;
bits<4> CRn; bits<4> CRn;
@ -3440,11 +3438,6 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1,
let Inst{23-20} = opc1; let Inst{23-20} = opc1;
} }
def : ARMPat<(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2),
(CDP2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, imm:$CRm,
imm:$opc2)>;
class ACI<dag oops, dag iops, string opc, string asm, class ACI<dag oops, dag iops, string opc, string asm,
IndexMode im = IndexModeNone> IndexMode im = IndexModeNone>
: InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary, : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
@ -3551,10 +3544,10 @@ defm STC2 : LdStCop<0b1111, 0, (ins), "stc2", "">;
// Move between coprocessor and ARM core register -- for disassembly only // Move between coprocessor and ARM core register -- for disassembly only
// //
class MovRCopro<string opc, bit direction, dag oops, dag iops> class MovRCopro<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
: ABI<0b1110, oops, iops, NoItinerary, opc, : ABI<0b1110, oops, iops, NoItinerary, opc,
"\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{20} = direction; let Inst{20} = direction;
let Inst{4} = 1; let Inst{4} = 1;
@ -3574,23 +3567,23 @@ class MovRCopro<string opc, bit direction, dag oops, dag iops>
} }
def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, (outs),
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
i32imm:$opc2)>; c_imm:$CRm, i32imm:$opc2),
[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)]>;
def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, (outs GPR:$Rt),
c_imm:$CRn, c_imm:$CRm, i32imm:$opc2)>; (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
i32imm:$opc2), []>;
def : ARMPat<(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2),
(MCR imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, imm:$CRm, imm:$opc2)>;
def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
(MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; (MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
class MovRCopro2<string opc, bit direction, dag oops, dag iops> class MovRCopro2<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
: ABXI<0b1110, oops, iops, NoItinerary, : ABXI<0b1110, oops, iops, NoItinerary,
!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{20} = direction; let Inst{20} = direction;
let Inst{4} = 1; let Inst{4} = 1;
@ -3611,27 +3604,25 @@ class MovRCopro2<string opc, bit direction, dag oops, dag iops>
} }
def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */, def MCR2 : MovRCopro2<"mcr2", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, (outs),
GPR:$Rt, c_imm:$CRn, c_imm:$CRm, (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
i32imm:$opc2)>; c_imm:$CRm, i32imm:$opc2),
[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)]>;
def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */, def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, (outs GPR:$Rt),
c_imm:$CRn, c_imm:$CRm, (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm,
i32imm:$opc2)>; i32imm:$opc2), []>;
def : ARMV5TPat<(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2),
(MCR2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)>;
def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
imm:$CRm, imm:$opc2), imm:$CRm, imm:$opc2),
(MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; (MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
class MovRRCopro<string opc, bit direction> class MovRRCopro<string opc, bit direction,
list<dag> pattern = [/* For disassembly only */]>
: ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm), GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;
let Inst{20} = direction; let Inst{20} = direction;
@ -3648,18 +3639,16 @@ class MovRRCopro<string opc, bit direction>
let Inst{3-0} = CRm; let Inst{3-0} = CRm;
} }
def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>; def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
[(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
imm:$CRm)]>;
def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
def : ARMV5TEPat<(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, class MovRRCopro2<string opc, bit direction,
imm:$CRm), list<dag> pattern = [/* For disassembly only */]>
(MCRR imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
class MovRRCopro2<string opc, bit direction>
: ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1, : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc1,
GPR:$Rt, GPR:$Rt2, c_imm:$CRm), GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
NoItinerary, !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{31-28} = 0b1111; let Inst{31-28} = 0b1111;
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;
let Inst{20} = direction; let Inst{20} = direction;
@ -3677,12 +3666,11 @@ class MovRRCopro2<string opc, bit direction>
let Inst{3-0} = CRm; let Inst{3-0} = CRm;
} }
def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */>; def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
imm:$CRm)]>;
def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>; def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
def : ARMV6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
(MCRR2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Move between special register and ARM core register -- for disassembly only // Move between special register and ARM core register -- for disassembly only
// //

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@ -1352,9 +1352,10 @@ def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
// Move between coprocessor and ARM core register -- for disassembly only // Move between coprocessor and ARM core register -- for disassembly only
// //
class tMovRCopro<string opc, bit direction, dag oops, dag iops> class tMovRCopro<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
: T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> { pattern> {
let Inst{27-24} = 0b1110; let Inst{27-24} = 0b1110;
let Inst{20} = direction; let Inst{20} = direction;
let Inst{4} = 1; let Inst{4} = 1;
@ -1375,24 +1376,24 @@ class tMovRCopro<string opc, bit direction, dag oops, dag iops>
} }
def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn, (outs),
c_imm:$CRm, i32imm:$opc2)>; (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2),
[(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)]>;
def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, (outs GPR:$Rt),
c_imm:$CRm, i32imm:$opc2)>; (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
[]>;
def : Pat<(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2),
(tMCR imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)>, Requires<[IsThumb, HasV6T2]>;
def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
(tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>, (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
Requires<[IsThumb, HasV6T2]>; Requires<[IsThumb, HasV6T2]>;
class tMovRRCopro<string opc, bit direction> class tMovRRCopro<string opc, bit direction,
list<dag> pattern = [/* For disassembly only */]>
: T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1100; let Inst{27-24} = 0b1100;
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;
let Inst{20} = direction; let Inst{20} = direction;
@ -1410,20 +1411,19 @@ class tMovRRCopro<string opc, bit direction>
let Inst{3-0} = CRm; let Inst{3-0} = CRm;
} }
def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>; def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
[(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
imm:$CRm)]>;
def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
def : Pat<(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
(tMCRR imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>,
Requires<[IsThumb, HasV6T2]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Other Coprocessor Instructions. For disassembly only. // Other Coprocessor Instructions. For disassembly only.
// //
def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
"cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> { [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
let Inst{27-24} = 0b1110; let Inst{27-24} = 0b1110;
bits<4> opc1; bits<4> opc1;
@ -1442,11 +1442,6 @@ def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
let Inst{23-20} = opc1; let Inst{23-20} = opc1;
} }
def : Pat<(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2),
(tCDP imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)>, Requires<[IsThumb, HasV6T2]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TLS Instructions // TLS Instructions
// //

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@ -3347,9 +3347,10 @@ def t2MSR : T2SpecialReg<0b111100111000 /* op31-20 */, 0b10 /* op15-14 */,
// Move between coprocessor and ARM core register -- for disassembly only // Move between coprocessor and ARM core register -- for disassembly only
// //
class t2MovRCopro<string opc, bit direction, dag oops, dag iops> class t2MovRCopro<string opc, bit direction, dag oops, dag iops,
list<dag> pattern>
: T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), : T2Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
[/* For disassembly only; pattern left blank */]> { pattern> {
let Inst{27-24} = 0b1110; let Inst{27-24} = 0b1110;
let Inst{20} = direction; let Inst{20} = direction;
let Inst{4} = 1; let Inst{4} = 1;
@ -3371,23 +3372,21 @@ class t2MovRCopro<string opc, bit direction, dag oops, dag iops>
def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */, def t2MCR2 : t2MovRCopro<"mcr2", 0 /* from ARM core register to coprocessor */,
(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn, (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>; c_imm:$CRm, i32imm:$opc2),
[(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)]>;
def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */, def t2MRC2 : t2MovRCopro<"mrc2", 1 /* from coprocessor to ARM core register */,
(outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
c_imm:$CRm, i32imm:$opc2)>; c_imm:$CRm, i32imm:$opc2), []>;
def : T2v6Pat<(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2),
(t2MCR2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
imm:$CRm, imm:$opc2)>;
def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
imm:$CRm, imm:$opc2), imm:$CRm, imm:$opc2),
(t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>;
class t2MovRRCopro<string opc, bit direction> class t2MovRRCopro<string opc, bit direction,
list<dag> pattern = [/* For disassembly only */]>
: T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
!strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
[/* For disassembly only; pattern left blank */]> {
let Inst{27-24} = 0b1100; let Inst{27-24} = 0b1100;
let Inst{23-21} = 0b010; let Inst{23-21} = 0b010;
let Inst{20} = direction; let Inst{20} = direction;
@ -3406,13 +3405,12 @@ class t2MovRRCopro<string opc, bit direction>
} }
def t2MCRR2 : t2MovRRCopro<"mcrr2", def t2MCRR2 : t2MovRRCopro<"mcrr2",
0 /* from ARM core register to coprocessor */>; 0 /* from ARM core register to coprocessor */,
[(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt,
GPR:$Rt2, imm:$CRm)]>;
def t2MRRC2 : t2MovRRCopro<"mrrc2", def t2MRRC2 : t2MovRRCopro<"mrrc2",
1 /* from coprocessor to ARM core register */>; 1 /* from coprocessor to ARM core register */>;
def : T2v6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
(t2MCRR2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm)>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Other Coprocessor Instructions. For disassembly only. // Other Coprocessor Instructions. For disassembly only.
// //
@ -3420,7 +3418,8 @@ def : T2v6Pat<(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, imm:$CRm),
def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
"cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
[/* For disassembly only; pattern left blank */]> { [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)]> {
let Inst{27-24} = 0b1110; let Inst{27-24} = 0b1110;
bits<4> opc1; bits<4> opc1;
@ -3438,8 +3437,3 @@ def t2CDP2 : T2Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
let Inst{19-16} = CRn; let Inst{19-16} = CRn;
let Inst{23-20} = opc1; let Inst{23-20} = opc1;
} }
def : T2v6Pat<(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2),
(t2CDP2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
imm:$CRm, imm:$opc2)>;