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Add asserts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129995 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2011-04-22 16:44:29 +00:00
parent b20a8fc8a6
commit 0a6ea83f39
1 changed files with 2 additions and 0 deletions
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2
lib/Target/ARM/ARMAsmPrinter.cpp
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@ -180,6 +180,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
else {
unsigned Reg = MLoc.getReg();
if (Reg >= ARM::S0 && Reg <= ARM::S31) {
assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
// S registers are described as bit-pieces of a register
// S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
// S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
@ -210,6 +211,7 @@ void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc) const {
EmitULEB128(0);
}
} else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
// Q registers Q0-Q15 are described by composing two D registers together.
// Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1) DW_OP_piece(8)