mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
revert r97807, it introduced build warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97869 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
e68bd74245
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0a7f442314
@ -129,15 +129,15 @@ SelectAddrRegReg(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index) {
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N.getOpcode() == ISD::TargetGlobalAddress)
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return false; // direct calls.
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if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
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N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
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return false; // jump tables.
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int32_t imm = 0;
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if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
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if (isIntS32Immediate(N.getOperand(1), imm))
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return false; // r+i
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if (N.getOperand(0).getOpcode() == ISD::TargetJumpTable ||
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N.getOperand(1).getOpcode() == ISD::TargetJumpTable)
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return false; // jump tables.
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Base = N.getOperand(1);
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Index = N.getOperand(0);
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return true;
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@ -138,13 +138,6 @@ MBlazeTargetLowering::MBlazeTargetLowering(MBlazeTargetMachine &TM)
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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// Variable Argument support
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::VAARG, MVT::Other, Expand);
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setOperationAction(ISD::VACOPY, MVT::Other, Expand);
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// Operations not directly supported by MBlaze.
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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@ -193,7 +186,6 @@ SDValue MBlazeTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
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case ISD::VASTART: return LowerVASTART(Op, DAG);
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}
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return SDValue();
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}
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@ -448,6 +440,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
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ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
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Constant *C = N->getConstVal();
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SDValue Zero = DAG.getConstant(0, PtrVT);
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// FIXME there isn't actually debug info here
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DebugLoc dl = Op.getDebugLoc();
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SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
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@ -455,121 +448,12 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(MBlazeISD::Wrap, dl, MVT::i32, CP);
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}
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SDValue MBlazeTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) {
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DebugLoc dl = Op.getDebugLoc();
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SDValue FI = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
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// vastart just stores the address of the VarArgsFrameIndex slot into the
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// memory location argument.
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const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
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return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), SV, 0,
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false, false, 0);
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}
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//===----------------------------------------------------------------------===//
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// Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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#include "MBlazeGenCallingConv.inc"
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static bool CC_MBlaze2(unsigned ValNo, EVT ValVT,
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EVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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static const unsigned RegsSize=6;
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static const unsigned IntRegs[] = {
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MBlaze::R5, MBlaze::R6, MBlaze::R7,
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MBlaze::R8, MBlaze::R9, MBlaze::R10
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};
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static const unsigned FltRegs[] = {
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MBlaze::F5, MBlaze::F6, MBlaze::F7,
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MBlaze::F8, MBlaze::F9, MBlaze::F10
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};
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unsigned Reg=0;
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//unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, RegsSize);
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// Promote i8 and i16
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if (LocVT == MVT::i8 || LocVT == MVT::i16) {
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LocVT = MVT::i32;
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if (ArgFlags.isSExt())
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LocInfo = CCValAssign::SExt;
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else if (ArgFlags.isZExt())
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LocInfo = CCValAssign::ZExt;
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else
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LocInfo = CCValAssign::AExt;
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}
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if (ValVT == MVT::i32) {
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Reg = State.AllocateReg(IntRegs, RegsSize);
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LocVT = MVT::i32;
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} else if (ValVT == MVT::f32) {
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Reg = State.AllocateReg(FltRegs, RegsSize);
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LocVT = MVT::f32;
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}
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if (!Reg) {
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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} else {
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
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}
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return false; // CC must always match
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}
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static bool CC_MBlaze_VarArg(unsigned ValNo, EVT ValVT,
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EVT LocVT, CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State) {
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static const unsigned RegsSize=6;
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static const unsigned IntRegs[] = {
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MBlaze::R5, MBlaze::R6, MBlaze::R7,
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MBlaze::R8, MBlaze::R9, MBlaze::R10
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};
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static const unsigned FltRegs[] = {
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MBlaze::F5, MBlaze::F6, MBlaze::F7,
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MBlaze::F8, MBlaze::F9, MBlaze::F10
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};
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// Promote i8 and i16
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if (LocVT == MVT::i8 || LocVT == MVT::i16) {
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LocVT = MVT::i32;
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if (ArgFlags.isSExt())
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LocInfo = CCValAssign::SExt;
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else if (ArgFlags.isZExt())
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LocInfo = CCValAssign::ZExt;
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else
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LocInfo = CCValAssign::AExt;
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}
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if (ValVT == MVT::i32) {
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if (unsigned Reg = State.AllocateReg(IntRegs, RegsSize)) {
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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State.AllocateStack(SizeInBytes, SizeInBytes);
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
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return false;
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}
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} else if (ValVT == MVT::f32) {
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if (unsigned Reg = State.AllocateReg(FltRegs, RegsSize)) {
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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State.AllocateStack(SizeInBytes, SizeInBytes);
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State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
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return false;
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}
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}
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unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
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unsigned Off = State.AllocateStack(SizeInBytes, SizeInBytes);
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State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
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return false;
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}
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//===----------------------------------------------------------------------===//
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// Call Calling Convention Implementation
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//===----------------------------------------------------------------------===//
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@ -584,9 +468,6 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) {
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// MBlaze does not yet support tail call optimization
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isTailCall = false;
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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@ -594,7 +475,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
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*DAG.getContext());
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CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze2);
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CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze);
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = CCInfo.getNextStackOffset();
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@ -606,7 +487,7 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
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// First/LastArgStackLoc contains the first/last
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// "at stack" argument location.
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int LastArgStackLoc = 0;
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unsigned FirstStackArgLoc = 0;
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unsigned FirstStackArgLoc = 4;
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// Walk the register/memloc assignments, inserting copies/loads.
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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@ -627,6 +508,9 @@ LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
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case CCValAssign::AExt:
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Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg);
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break;
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case CCValAssign::BCvt:
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Arg = DAG.getNode(ISD::BIT_CONVERT, dl, RegVT, Arg);
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break;
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}
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// Arguments that can be passed on register must be kept at
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@ -745,6 +629,7 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallingConv::ID CallConv,
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/// LowerFormalArguments - transform physical registers into
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/// virtual registers and generate load operations for
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/// arguments places on the stack.
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/// TODO: isVarArg
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SDValue MBlazeTargetLowering::
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LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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@ -755,23 +640,16 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
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unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
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VarArgsFrameIndex = 0;
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// Used with vargs to acumulate store chains.
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std::vector<SDValue> OutChains;
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// Keep track of the last register used for arguments
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unsigned ArgRegEnd = 0;
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// Assign locations to all of the incoming arguments.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
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ArgLocs, *DAG.getContext());
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CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze2);
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CCInfo.AnalyzeFormalArguments(Ins, CC_MBlaze);
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SDValue StackPtr;
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unsigned FirstStackArgLoc = 0;
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unsigned FirstStackArgLoc = 4;
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for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
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CCValAssign &VA = ArgLocs[i];
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@ -779,7 +657,6 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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// Arguments stored on registers
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if (VA.isRegLoc()) {
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EVT RegVT = VA.getLocVT();
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ArgRegEnd = VA.getLocReg();
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TargetRegisterClass *RC = 0;
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if (RegVT == MVT::i32)
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@ -791,13 +668,12 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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// Transform the arguments stored on
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// physical registers into virtual ones
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unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
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unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
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// If this is an 8 or 16-bit value, it has been passed promoted
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// to 32 bits. Insert an assert[sz]ext to capture this, then
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// truncate to the right size. If if is a floating point value
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// then convert to the correct type.
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// truncate to the right size.
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if (VA.getLocInfo() != CCValAssign::Full) {
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unsigned Opcode = 0;
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if (VA.getLocInfo() == CCValAssign::SExt)
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@ -812,14 +688,35 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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InVals.push_back(ArgValue);
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// To meet ABI, when VARARGS are passed on registers, the registers
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// must have their values written to the caller stack frame.
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if (isVarArg) {
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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// The stack pointer offset is relative to the caller stack frame.
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// Since the real stack size is unknown here, a negative SPOffset
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// is used so there's a way to adjust these offsets when the stack
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// size get known (on EliminateFrameIndex). A dummy SPOffset is
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// used instead of a direct negative address (which is recorded to
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// be used on emitPrologue) to avoid mis-calc of the first stack
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// offset on PEI::calculateFrameObjectOffsets.
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// Arguments are always 32-bit.
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int FI = MFI->CreateFixedObject(4, 0, true, false);
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MBlazeFI->recordStoreVarArgsFI(FI, -(FirstStackArgLoc+(i*4)));
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SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
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// emit ISD::STORE whichs stores the
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// parameter value to a stack Location
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InVals.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
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false, false, 0));
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}
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} else { // VA.isRegLoc()
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// sanity check
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assert(VA.isMemLoc());
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// The last argument is not a register
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ArgRegEnd = 0;
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// The stack pointer offset is relative to the caller stack frame.
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// Since the real stack size is unknown here, a negative SPOffset
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// is used so there's a way to adjust these offsets when the stack
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@ -840,47 +737,6 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
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}
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}
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// To meet ABI, when VARARGS are passed on registers, the registers
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// must have their values written to the caller stack frame. If the last
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// argument was placed in the stack, there's no need to save any register.
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if ((isVarArg) && ArgRegEnd) {
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if (StackPtr.getNode() == 0)
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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// The last register argument that must be saved is MBlaze::R10
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TargetRegisterClass *RC = MBlaze::CPURegsRegisterClass;
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unsigned Begin = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R5);
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unsigned Start = MBlazeRegisterInfo::getRegisterNumbering(ArgRegEnd+1);
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unsigned End = MBlazeRegisterInfo::getRegisterNumbering(MBlaze::R10);
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unsigned StackLoc = ArgLocs.size()-1 + (Start - Begin);
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for (; Start <= End; ++Start, ++StackLoc) {
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unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
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unsigned LiveReg = MF.addLiveIn(Reg, RC);
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SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
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int FI = MFI->CreateFixedObject(4, 0, true, false);
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MBlazeFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
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SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
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OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, NULL, 0,
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false, false, 0));
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// Record the frame index of the first variable argument
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// which is a value necessary to VASTART.
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if (!VarArgsFrameIndex)
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VarArgsFrameIndex = FI;
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}
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}
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// All stores are grouped in one node to allow the matching between
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// the size of Ins and InVals. This only happens when on varg functions
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if (!OutChains.empty()) {
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OutChains.push_back(Chain);
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Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
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&OutChains[0], OutChains.size());
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}
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return Chain;
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}
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@ -63,8 +63,6 @@ namespace llvm {
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//===--------------------------------------------------------------------===//
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class MBlazeTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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public:
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explicit MBlazeTargetLowering(MBlazeTargetMachine &TM);
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@ -98,7 +96,6 @@ namespace llvm {
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SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
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SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
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virtual SDValue
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LowerFormalArguments(SDValue Chain,
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@ -85,47 +85,6 @@ unsigned MBlazeRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
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return 0; // Not reached
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}
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/// getRegisterFromNumbering - Given the enum value for some register, e.g.
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/// MBlaze::R0, return the number that it corresponds to (e.g. 0).
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unsigned MBlazeRegisterInfo::getRegisterFromNumbering(unsigned Reg) {
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switch (Reg) {
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case 0 : return MBlaze::R0;
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case 1 : return MBlaze::R1;
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case 2 : return MBlaze::R2;
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case 3 : return MBlaze::R3;
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case 4 : return MBlaze::R4;
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case 5 : return MBlaze::R5;
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case 6 : return MBlaze::R6;
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case 7 : return MBlaze::R7;
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case 8 : return MBlaze::R8;
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case 9 : return MBlaze::R9;
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case 10 : return MBlaze::R10;
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case 11 : return MBlaze::R11;
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case 12 : return MBlaze::R12;
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case 13 : return MBlaze::R13;
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case 14 : return MBlaze::R14;
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case 15 : return MBlaze::R15;
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case 16 : return MBlaze::R16;
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case 17 : return MBlaze::R17;
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case 18 : return MBlaze::R18;
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case 19 : return MBlaze::R19;
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case 20 : return MBlaze::R20;
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case 21 : return MBlaze::R21;
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case 22 : return MBlaze::R22;
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case 23 : return MBlaze::R23;
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case 24 : return MBlaze::R24;
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case 25 : return MBlaze::R25;
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||||
case 26 : return MBlaze::R26;
|
||||
case 27 : return MBlaze::R27;
|
||||
case 28 : return MBlaze::R28;
|
||||
case 29 : return MBlaze::R29;
|
||||
case 30 : return MBlaze::R30;
|
||||
case 31 : return MBlaze::R31;
|
||||
default: llvm_unreachable("Unknown register number!");
|
||||
}
|
||||
return 0; // Not reached
|
||||
}
|
||||
|
||||
unsigned MBlazeRegisterInfo::getPICCallReg() {
|
||||
return MBlaze::R20;
|
||||
}
|
||||
@ -221,9 +180,9 @@ void MBlazeRegisterInfo::adjustMBlazeStackFrame(MachineFunction &MF) const {
|
||||
}
|
||||
|
||||
if (MFI->hasCalls()) {
|
||||
MBlazeFI->setRAStackOffset(0);
|
||||
MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true),
|
||||
StackOffset);
|
||||
MBlazeFI->setRAStackOffset(StackOffset);
|
||||
TopCPUSavedRegOff = StackOffset;
|
||||
StackOffset += RegSize;
|
||||
}
|
||||
@ -286,7 +245,7 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
|
||||
|
||||
// as explained on LowerFormalArguments, detect negative offsets
|
||||
// and adjust SPOffsets considering the final stack size.
|
||||
int Offset = (spOffset < 0) ? (stackSize - spOffset) : (spOffset + 4);
|
||||
int Offset = ((spOffset < 0) ? (stackSize + (-(spOffset+4))) : (spOffset));
|
||||
Offset += MI.getOperand(oi).getImm();
|
||||
|
||||
DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
|
||||
@ -313,7 +272,6 @@ emitPrologue(MachineFunction &MF) const {
|
||||
|
||||
// No need to allocate space on the stack.
|
||||
if (StackSize == 0 && !MFI->hasCalls()) return;
|
||||
if (StackSize < 28 && MFI->hasCalls()) StackSize = 28;
|
||||
|
||||
int FPOffset = MBlazeFI->getFPStackOffset();
|
||||
int RAOffset = MBlazeFI->getRAStackOffset();
|
||||
@ -349,6 +307,9 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
|
||||
MBlazeFunctionInfo *MBlazeFI = MF.getInfo<MBlazeFunctionInfo>();
|
||||
DebugLoc dl = MBBI->getDebugLoc();
|
||||
|
||||
// Get the number of bytes from FrameInfo
|
||||
int NumBytes = (int) MFI->getStackSize();
|
||||
|
||||
// Get the FI's where RA and FP are saved.
|
||||
int FPOffset = MBlazeFI->getFPStackOffset();
|
||||
int RAOffset = MBlazeFI->getRAStackOffset();
|
||||
@ -372,15 +333,11 @@ emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {
|
||||
.addImm(RAOffset).addReg(MBlaze::R1);
|
||||
}
|
||||
|
||||
// Get the number of bytes from FrameInfo
|
||||
int StackSize = (int) MFI->getStackSize();
|
||||
if (StackSize < 28 && MFI->hasCalls()) StackSize = 28;
|
||||
|
||||
// adjust stack.
|
||||
// addi R1, R1, imm
|
||||
if (StackSize) {
|
||||
if (NumBytes) {
|
||||
BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDI), MBlaze::R1)
|
||||
.addReg(MBlaze::R1).addImm(StackSize);
|
||||
.addReg(MBlaze::R1).addImm(NumBytes);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -43,7 +43,6 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
|
||||
/// getRegisterNumbering - Given the enum value for some register, e.g.
|
||||
/// MBlaze::RA, return the number that it corresponds to (e.g. 31).
|
||||
static unsigned getRegisterNumbering(unsigned RegEnum);
|
||||
static unsigned getRegisterFromNumbering(unsigned RegEnum);
|
||||
|
||||
/// Get PIC indirect call register
|
||||
static unsigned getPICCallReg();
|
||||
@ -83,11 +82,6 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
|
||||
unsigned getEHExceptionRegister() const;
|
||||
unsigned getEHHandlerRegister() const;
|
||||
|
||||
/// targetHandlesStackFrameRounding - Returns true if the target is
|
||||
/// responsible for rounding up the stack frame (probably at emitPrologue
|
||||
/// time).
|
||||
bool targetHandlesStackFrameRounding() const { return true; }
|
||||
|
||||
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
|
||||
};
|
||||
|
||||
|
@ -101,7 +101,7 @@ define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
|
||||
i32 %g) {
|
||||
; CHECK: params7_32bitret:
|
||||
ret i32 %g
|
||||
; CHECK: {{lwi? r3, r1, 32}}
|
||||
; CHECK: {{lwi? r3, r1, 8}}
|
||||
; CHECK-NOT: {{.* r4, .*, .*}}
|
||||
; CHECK: rtsd
|
||||
}
|
||||
@ -110,7 +110,7 @@ define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
|
||||
i32 %g, i32 %h) {
|
||||
; CHECK: params8_32bitret:
|
||||
ret i32 %h
|
||||
; CHECK: {{lwi? r3, r1, 36}}
|
||||
; CHECK: {{lwi? r3, r1, 12}}
|
||||
; CHECK-NOT: {{.* r4, .*, .*}}
|
||||
; CHECK: rtsd
|
||||
}
|
||||
@ -119,7 +119,7 @@ define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
|
||||
i32 %g, i32 %h, i32 %i) {
|
||||
; CHECK: params9_32bitret:
|
||||
ret i32 %i
|
||||
; CHECK: {{lwi? r3, r1, 40}}
|
||||
; CHECK: {{lwi? r3, r1, 16}}
|
||||
; CHECK-NOT: {{.* r4, .*, .*}}
|
||||
; CHECK: rtsd
|
||||
}
|
||||
@ -128,7 +128,7 @@ define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
|
||||
i32 %g, i32 %h, i32 %i, i32 %j) {
|
||||
; CHECK: params10_32bitret:
|
||||
ret i32 %j
|
||||
; CHECK: {{lwi? r3, r1, 44}}
|
||||
; CHECK: {{lwi? r3, r1, 20}}
|
||||
; CHECK-NOT: {{.* r4, .*, .*}}
|
||||
; CHECK: rtsd
|
||||
}
|
||||
@ -243,7 +243,7 @@ define void @testing() {
|
||||
|
||||
%tmp.11 = call i32 @params7_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
|
||||
i32 6, i32 7)
|
||||
; CHECK: {{swi? .*, r1, 28}}
|
||||
; CHECK: {{swi? .*, r1, 4}}
|
||||
; CHECK: {{.* r5, .*, .*}}
|
||||
; CHECK: {{.* r6, .*, .*}}
|
||||
; CHECK: {{.* r7, .*, .*}}
|
||||
@ -259,8 +259,8 @@ define void @testing() {
|
||||
|
||||
%tmp.12 = call i32 @params8_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
|
||||
i32 6, i32 7, i32 8)
|
||||
; CHECK: {{swi? .*, r1, 28}}
|
||||
; CHECK: {{swi? .*, r1, 32}}
|
||||
; CHECK: {{swi? .*, r1, 4}}
|
||||
; CHECK: {{swi? .*, r1, 8}}
|
||||
; CHECK: {{.* r5, .*, .*}}
|
||||
; CHECK: {{.* r6, .*, .*}}
|
||||
; CHECK: {{.* r7, .*, .*}}
|
||||
@ -276,9 +276,9 @@ define void @testing() {
|
||||
|
||||
%tmp.13 = call i32 @params9_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
|
||||
i32 6, i32 7, i32 8, i32 9)
|
||||
; CHECK: {{swi? .*, r1, 28}}
|
||||
; CHECK: {{swi? .*, r1, 32}}
|
||||
; CHECK: {{swi? .*, r1, 36}}
|
||||
; CHECK: {{swi? .*, r1, 4}}
|
||||
; CHECK: {{swi? .*, r1, 8}}
|
||||
; CHECK: {{swi? .*, r1, 12}}
|
||||
; CHECK: {{.* r5, .*, .*}}
|
||||
; CHECK: {{.* r6, .*, .*}}
|
||||
; CHECK: {{.* r7, .*, .*}}
|
||||
@ -294,10 +294,10 @@ define void @testing() {
|
||||
|
||||
%tmp.14 = call i32 @params10_32bitret(i32 1, i32 2, i32 3, i32 4, i32 5,
|
||||
i32 6, i32 7, i32 8, i32 9, i32 10)
|
||||
; CHECK: {{swi? .*, r1, 28}}
|
||||
; CHECK: {{swi? .*, r1, 32}}
|
||||
; CHECK: {{swi? .*, r1, 36}}
|
||||
; CHECK: {{swi? .*, r1, 40}}
|
||||
; CHECK: {{swi? .*, r1, 4}}
|
||||
; CHECK: {{swi? .*, r1, 8}}
|
||||
; CHECK: {{swi? .*, r1, 12}}
|
||||
; CHECK: {{swi? .*, r1, 16}}
|
||||
; CHECK: {{.* r5, .*, .*}}
|
||||
; CHECK: {{.* r6, .*, .*}}
|
||||
; CHECK: {{.* r7, .*, .*}}
|
||||
|
Loading…
Reference in New Issue
Block a user