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[AArch64 NEON]Implment loading vector constant form constant pool.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197551 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Qin 2013-12-18 06:26:04 +00:00
parent 5a445395de
commit 0a9ff8776b
7 changed files with 163 additions and 10 deletions
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9
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
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@ -1113,15 +1113,6 @@ SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
return CurDAG->SelectNodeTo(Node, AArch64::ADDxxi_lsl0_s, PtrTy,
TFI, CurDAG->getTargetConstant(0, PtrTy));
}
case ISD::ConstantPool: {
// Constant pools are fine, just create a Target entry.
ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Node);
const Constant *C = CN->getConstVal();
SDValue CP = CurDAG->getTargetConstantPool(C, CN->getValueType(0));
ReplaceUses(SDValue(Node, 0), CP);
return NULL;
}
case ISD::Constant: {
SDNode *ResNode = 0;
if (cast<ConstantSDNode>(Node)->getZExtValue() == 0) {

32
lib/Target/AArch64/AArch64ISelLowering.cpp
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@ -140,6 +140,7 @@ AArch64TargetLowering::AArch64TargetLowering(AArch64TargetMachine &TM)
setOperationAction(ISD::VAARG, MVT::Other, Expand);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
setOperationAction(ISD::ROTL, MVT::i32, Expand);
setOperationAction(ISD::ROTL, MVT::i64, Expand);
@ -2268,6 +2269,36 @@ AArch64TargetLowering::LowerGlobalAddressELF(SDValue Op,
}
}
SDValue
AArch64TargetLowering::LowerConstantPool(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
EVT PtrVT = getPointerTy();
ConstantPoolSDNode *CN = cast<ConstantPoolSDNode>(Op);
const Constant *C = CN->getConstVal();
switch(getTargetMachine().getCodeModel()) {
case CodeModel::Small:
// The most efficient code is PC-relative anyway for the small memory model,
// so we don't need to worry about relocation model.
return DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
DAG.getTargetConstantPool(C, PtrVT, 0, 0,
AArch64II::MO_NO_FLAG),
DAG.getTargetConstantPool(C, PtrVT, 0, 0,
AArch64II::MO_LO12),
DAG.getConstant(CN->getAlignment(), MVT::i32));
case CodeModel::Large:
return DAG.getNode(
AArch64ISD::WrapperLarge, DL, PtrVT,
DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G3),
DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G2_NC),
DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G1_NC),
DAG.getTargetConstantPool(C, PtrVT, 0, 0, AArch64II::MO_ABS_G0_NC));
default:
llvm_unreachable("Only small and large code models supported now");
}
}
SDValue AArch64TargetLowering::LowerTLSDescCall(SDValue SymAddr,
SDValue DescAddr,
SDLoc DL,
@ -2898,6 +2929,7 @@ AArch64TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
case ISD::BR_CC: return LowerBR_CC(Op, DAG);
case ISD::GlobalAddress: return LowerGlobalAddressELF(Op, DAG);
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
case ISD::SELECT: return LowerSELECT(Op, DAG);

2
lib/Target/AArch64/AArch64ISelLowering.h
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@ -306,6 +306,8 @@ public:
SDValue LowerGlobalAddressELFLarge(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerTLSDescCall(SDValue SymAddr, SDValue DescAddr, SDLoc DL,
SelectionDAG &DAG) const;
SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;

1
lib/Target/AArch64/AArch64InstrInfo.td
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@ -4539,6 +4539,7 @@ def : ADRP_ADD<A64WrapperSmall, texternalsym>;
def : ADRP_ADD<A64WrapperSmall, tglobaladdr>;
def : ADRP_ADD<A64WrapperSmall, tglobaltlsaddr>;
def : ADRP_ADD<A64WrapperSmall, tjumptable>;
def : ADRP_ADD<A64WrapperSmall, tconstpool>;
//===----------------------------------------------------------------------===//
// GOT access patterns

44
lib/Target/AArch64/AArch64InstrNEON.td
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@ -69,6 +69,50 @@ def SDT_assertext : SDTypeProfile<1, 1,
def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
//===----------------------------------------------------------------------===//
// Addressing-mode instantiations
//===----------------------------------------------------------------------===//
multiclass ls_64_pats<dag address, dag Base, dag Offset, ValueType Ty> {
defm : ls_neutral_pats<LSFP64_LDR, LSFP64_STR, Base,
!foreach(decls.pattern, Offset,
!subst(OFFSET, dword_uimm12, decls.pattern)),
!foreach(decls.pattern, address,
!subst(OFFSET, dword_uimm12,
!subst(ALIGN, min_align8, decls.pattern))),
Ty>;
}
multiclass ls_128_pats<dag address, dag Base, dag Offset, ValueType Ty> {
defm : ls_neutral_pats<LSFP128_LDR, LSFP128_STR, Base,
!foreach(decls.pattern, Offset,
!subst(OFFSET, qword_uimm12, decls.pattern)),
!foreach(decls.pattern, address,
!subst(OFFSET, qword_uimm12,
!subst(ALIGN, min_align16, decls.pattern))),
Ty>;
}
multiclass uimm12_neon_pats<dag address, dag Base, dag Offset> {
defm : ls_64_pats<address, Base, Offset, v8i8>;
defm : ls_64_pats<address, Base, Offset, v4i16>;
defm : ls_64_pats<address, Base, Offset, v2i32>;
defm : ls_64_pats<address, Base, Offset, v1i64>;
defm : ls_64_pats<address, Base, Offset, v2f32>;
defm : ls_64_pats<address, Base, Offset, v1f64>;
defm : ls_128_pats<address, Base, Offset, v16i8>;
defm : ls_128_pats<address, Base, Offset, v8i16>;
defm : ls_128_pats<address, Base, Offset, v4i32>;
defm : ls_128_pats<address, Base, Offset, v2i64>;
defm : ls_128_pats<address, Base, Offset, v4f32>;
defm : ls_128_pats<address, Base, Offset, v2f64>;
}
defm : uimm12_neon_pats<(A64WrapperSmall
tconstpool:$Hi, tconstpool:$Lo12, ALIGN),
(ADRPxi tconstpool:$Hi), (i64 tconstpool:$Lo12)>;
//===----------------------------------------------------------------------===//
// Multiclasses
//===----------------------------------------------------------------------===//

4
test/CodeGen/AArch64/neon-mov.ll
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@ -210,7 +210,9 @@ define <2 x i32> @movi1d_1() {
declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
define <2 x i32> @movi1d() {
; CHECK: movi d1, #0xffffffff0000
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
; CHECK-NEXT: movi d1, #0xffffffff0000
%1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
ret <2 x i32> %1
}

81
test/CodeGen/AArch64/neon-simd-ldst-one.ll
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@ -37,6 +37,87 @@
%struct.float32x2x4_t = type { [4 x <2 x float>] }
%struct.float64x1x4_t = type { [4 x <1 x double>] }
define <16 x i8> @test_ld_from_poll_v16i8(<16 x i8> %a) {
; CHECK-LABEL: test_ld_from_poll_v16i8
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <16 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 2, i8 13, i8 14, i8 15, i8 16>
ret <16 x i8> %b
}
define <8 x i16> @test_ld_from_poll_v8i16(<8 x i16> %a) {
; CHECK-LABEL: test_ld_from_poll_v8i16
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <8 x i16> %a, <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
ret <8 x i16> %b
}
define <4 x i32> @test_ld_from_poll_v4i32(<4 x i32> %a) {
; CHECK-LABEL: test_ld_from_poll_v4i32
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <4 x i32> %a, <i32 1, i32 2, i32 3, i32 4>
ret <4 x i32> %b
}
define <2 x i64> @test_ld_from_poll_v2i64(<2 x i64> %a) {
; CHECK-LABEL: test_ld_from_poll_v2i64
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <2 x i64> %a, <i64 1, i64 2>
ret <2 x i64> %b
}
define <4 x float> @test_ld_from_poll_v4f32(<4 x float> %a) {
; CHECK-LABEL: test_ld_from_poll_v4f32
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = fadd <4 x float> %a, <float 1.0, float 2.0, float 3.0, float 4.0>
ret <4 x float> %b
}
define <2 x double> @test_ld_from_poll_v2f64(<2 x double> %a) {
; CHECK-LABEL: test_ld_from_poll_v2f64
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = fadd <2 x double> %a, <double 1.0, double 2.0>
ret <2 x double> %b
}
define <8 x i8> @test_ld_from_poll_v8i8(<8 x i8> %a) {
; CHECK-LABEL: test_ld_from_poll_v8i8
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <8 x i8> %a, <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>
ret <8 x i8> %b
}
define <4 x i16> @test_ld_from_poll_v4i16(<4 x i16> %a) {
; CHECK-LABEL: test_ld_from_poll_v4i16
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <4 x i16> %a, <i16 1, i16 2, i16 3, i16 4>
ret <4 x i16> %b
}
define <2 x i32> @test_ld_from_poll_v2i32(<2 x i32> %a) {
; CHECK-LABEL: test_ld_from_poll_v2i32
; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
; CHECK-NEXT: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:.{{[A-Z0-9_]+}}]
entry:
%b = add <2 x i32> %a, <i32 1, i32 2>
ret <2 x i32> %b
}
define <16 x i8> @test_vld1q_dup_s8(i8* %a) {
; CHECK-LABEL: test_vld1q_dup_s8
; CHECK: ld1r {{{v[0-9]+}}.16b}, [x0]