mirror of
https://github.com/c64scene-ar/llvm-6502.git
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split call handling out of X86SelectAddress into X86SelectCallAddress
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75228 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
8a537121cb
commit
0aa43de1d0
@ -90,7 +90,8 @@ private:
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bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT,
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unsigned &ResultReg);
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bool X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall);
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bool X86SelectAddress(Value *V, X86AddressMode &AM);
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bool X86SelectCallAddress(Value *V, X86AddressMode &AM);
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bool X86SelectLoad(Instruction *I);
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@ -318,7 +319,7 @@ bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT,
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/// X86SelectAddress - Attempt to fill in an address from the given value.
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///
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bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) {
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User *U = NULL;
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unsigned Opcode = Instruction::UserOp1;
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if (Instruction *I = dyn_cast<Instruction>(V)) {
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@ -333,22 +334,21 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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default: break;
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case Instruction::BitCast:
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// Look past bitcasts.
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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return X86SelectAddress(U->getOperand(0), AM);
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case Instruction::IntToPtr:
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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return X86SelectAddress(U->getOperand(0), AM);
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break;
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case Instruction::PtrToInt:
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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return X86SelectAddress(U->getOperand(0), AM);
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break;
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case Instruction::Alloca: {
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if (isCall) break;
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// Do static allocas.
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const AllocaInst *A = cast<AllocaInst>(V);
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DenseMap<const AllocaInst*, int>::iterator SI = StaticAllocaMap.find(A);
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@ -361,21 +361,19 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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}
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case Instruction::Add: {
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if (isCall) break;
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// Adds of constants are common and easy enough.
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if (ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) {
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uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue();
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// They have to fit in the 32-bit signed displacement field though.
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if (isInt32(Disp)) {
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AM.Disp = (uint32_t)Disp;
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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return X86SelectAddress(U->getOperand(0), AM);
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}
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}
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break;
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}
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case Instruction::GetElementPtr: {
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if (isCall) break;
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// Pattern-match simple GEPs.
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uint64_t Disp = (int32_t)AM.Disp;
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unsigned IndexReg = AM.IndexReg;
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@ -416,7 +414,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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AM.IndexReg = IndexReg;
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AM.Scale = Scale;
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AM.Disp = (uint32_t)Disp;
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return X86SelectAddress(U->getOperand(0), AM, isCall);
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return X86SelectAddress(U->getOperand(0), AM);
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unsupported_gep:
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// Ok, the GEP indices weren't all covered.
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break;
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@ -443,8 +441,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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// Okay, we've committed to selecting this global. Set up the basic address.
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AM.GV = GV;
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if (!isCall &&
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TM.getRelocationModel() == Reloc::PIC_ &&
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if (TM.getRelocationModel() == Reloc::PIC_ &&
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!Subtarget->is64Bit()) {
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// FIXME: How do we know Base.Reg is free??
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AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
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@ -452,7 +449,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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// If the ABI doesn't require an extra load, return a direct reference to
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// the global.
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if (!Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
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if (!Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
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if (Subtarget->isPICStyleRIPRel()) {
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// Use rip-relative addressing if we can. Above we verified that the
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// base and index registers are unused.
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@ -546,6 +543,155 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
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return false;
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}
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/// X86SelectCallAddress - Attempt to fill in an address from the given value.
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///
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bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) {
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User *U = NULL;
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unsigned Opcode = Instruction::UserOp1;
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if (Instruction *I = dyn_cast<Instruction>(V)) {
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Opcode = I->getOpcode();
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U = I;
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} else if (ConstantExpr *C = dyn_cast<ConstantExpr>(V)) {
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Opcode = C->getOpcode();
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U = C;
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}
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switch (Opcode) {
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default: break;
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case Instruction::BitCast:
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// Look past bitcasts.
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return X86SelectCallAddress(U->getOperand(0), AM);
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case Instruction::IntToPtr:
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return X86SelectCallAddress(U->getOperand(0), AM);
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break;
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case Instruction::PtrToInt:
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return X86SelectCallAddress(U->getOperand(0), AM);
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break;
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}
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// Handle constant address.
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if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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// Can't handle alternate code models yet.
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if (TM.getCodeModel() != CodeModel::Default &&
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TM.getCodeModel() != CodeModel::Small)
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return false;
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// RIP-relative addresses can't have additional register operands.
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if (Subtarget->isPICStyleRIPRel() &&
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(AM.Base.Reg != 0 || AM.IndexReg != 0))
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return false;
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// Can't handle TLS yet.
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if (GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV))
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if (GVar->isThreadLocal())
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return false;
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// Okay, we've committed to selecting this global. Set up the basic address.
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AM.GV = GV;
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// If the ABI doesn't require an extra load, return a direct reference to
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// the global.
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if (!Subtarget->GVRequiresExtraLoad(GV, TM, true)) {
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if (Subtarget->isPICStyleRIPRel()) {
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// Use rip-relative addressing if we can. Above we verified that the
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// base and index registers are unused.
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assert(AM.Base.Reg == 0 && AM.IndexReg == 0);
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AM.Base.Reg = X86::RIP;
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} else if (Subtarget->isPICStyleStub() &&
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TM.getRelocationModel() == Reloc::PIC_) {
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AM.GVOpFlags = X86II::MO_PIC_BASE_OFFSET;
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} else if (Subtarget->isPICStyleGOT()) {
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AM.GVOpFlags = X86II::MO_GOTOFF;
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}
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return true;
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}
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// Check to see if we've already materialized this stub loaded value into a
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// register in this block. If so, just reuse it.
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DenseMap<const Value*, unsigned>::iterator I = LocalValueMap.find(V);
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unsigned LoadReg;
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if (I != LocalValueMap.end() && I->second != 0) {
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LoadReg = I->second;
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} else {
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// Issue load from stub.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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X86AddressMode StubAM;
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StubAM.Base.Reg = AM.Base.Reg;
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StubAM.GV = GV;
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if (TLI.getPointerTy() == MVT::i64) {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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if (Subtarget->isPICStyleRIPRel()) {
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StubAM.GVOpFlags = X86II::MO_GOTPCREL;
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StubAM.Base.Reg = X86::RIP;
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}
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} else {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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if (Subtarget->isPICStyleGOT())
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StubAM.GVOpFlags = X86II::MO_GOT;
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else if (Subtarget->isPICStyleStub()) {
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// In darwin, we have multiple different stub types, and we have both
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// PIC and -mdynamic-no-pic. Determine whether we have a stub
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// reference and/or whether the reference is relative to the PIC base
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// or not.
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bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
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if (!GV->hasHiddenVisibility()) {
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// Non-hidden $non_lazy_ptr reference.
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StubAM.GVOpFlags = IsPIC ? X86II::MO_DARWIN_NONLAZY_PIC_BASE :
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X86II::MO_DARWIN_NONLAZY;
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} else {
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// Hidden $non_lazy_ptr reference.
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StubAM.GVOpFlags = IsPIC ? X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE:
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X86II::MO_DARWIN_HIDDEN_NONLAZY;
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}
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}
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}
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LoadReg = createResultReg(RC);
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addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = LoadReg;
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}
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// Now construct the final address. Note that the Disp, Scale,
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// and Index values may already be set here.
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AM.Base.Reg = LoadReg;
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AM.GV = 0;
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return true;
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}
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// If all else fails, try to materialize the value in a register.
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if (!AM.GV || !Subtarget->isPICStyleRIPRel()) {
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if (AM.Base.Reg == 0) {
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AM.Base.Reg = getRegForValue(V);
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return AM.Base.Reg != 0;
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}
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if (AM.IndexReg == 0) {
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assert(AM.Scale == 1 && "Scale with no index!");
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AM.IndexReg = getRegForValue(V);
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return AM.IndexReg != 0;
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}
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}
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return false;
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}
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/// X86SelectStore - Select and emit code to implement store instructions.
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bool X86FastISel::X86SelectStore(Instruction* I) {
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MVT VT;
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@ -553,7 +699,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(1), AM, false))
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if (!X86SelectAddress(I->getOperand(1), AM))
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return false;
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return X86FastEmitStore(VT, I->getOperand(0), AM);
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@ -567,7 +713,7 @@ bool X86FastISel::X86SelectLoad(Instruction *I) {
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return false;
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X86AddressMode AM;
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if (!X86SelectAddress(I->getOperand(0), AM, false))
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if (!X86SelectAddress(I->getOperand(0), AM))
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return false;
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unsigned ResultReg = 0;
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@ -1181,7 +1327,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
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// Materialize callee address in a register. FIXME: GV address can be
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// handled with a CALLpcrel32 instead.
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X86AddressMode CalleeAM;
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if (!X86SelectAddress(Callee, CalleeAM, true))
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if (!X86SelectCallAddress(Callee, CalleeAM))
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return false;
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unsigned CalleeOp = 0;
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GlobalValue *GV = 0;
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@ -1540,7 +1686,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) {
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// Materialize addresses with LEA instructions.
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if (isa<GlobalValue>(C)) {
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X86AddressMode AM;
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if (X86SelectAddress(C, AM, false)) {
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if (X86SelectAddress(C, AM)) {
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if (TLI.getPointerTy() == MVT::i32)
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Opc = X86::LEA32r;
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else
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@ -1595,7 +1741,7 @@ unsigned X86FastISel::TargetMaterializeAlloca(AllocaInst *C) {
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return 0;
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X86AddressMode AM;
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if (!X86SelectAddress(C, AM, false))
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if (!X86SelectAddress(C, AM))
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return 0;
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unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
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TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
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