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Add encodings for some of the thumb ADD instructions. Tests will come once the
asm parser can handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119860 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -195,7 +195,6 @@ def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
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[/* For disassembly only; pattern left blank */]>,
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[/* For disassembly only; pattern left blank */]>,
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T1Encoding<0b101111> {
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T1Encoding<0b101111> {
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bits<8> val;
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bits<8> val;
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let Inst{9-8} = 0b10;
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let Inst{9-8} = 0b10;
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let Inst{7-0} = val;
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let Inst{7-0} = val;
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}
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}
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@ -216,48 +215,77 @@ def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
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// For both thumb1 and thumb2.
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// For both thumb1 and thumb2.
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let isNotDuplicable = 1, isCodeGenOnly = 1 in
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let isNotDuplicable = 1, isCodeGenOnly = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}> {
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let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
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// A8.6.6 Rm = pc
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bits<3> dst;
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let Inst{6-3} = 0b1111;
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let Inst{2-0} = dst;
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}
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}
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// PC relative add.
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// PC relative add.
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, pc, $rhs", []>,
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"add\t$dst, pc, $rhs", []>,
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T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
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T1Encoding<{1,0,1,0,0,?}> {
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// A6.2 & A8.6.10
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// ADD rd, sp, #imm8
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bits<3> dst;
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// This is rematerializable, which is particularly useful for taking the
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bits<8> rhs;
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// address of locals.
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let Inst{10-8} = dst;
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let isReMaterializable = 1 in {
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let Inst{7-0} = rhs;
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, $sp, $rhs", []>,
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T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
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}
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}
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// ADD sp, sp, #imm7
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// ADD <Rd>, sp, #<imm8>
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// This is rematerializable, which is particularly useful for taking the
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// address of locals.
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let isReMaterializable = 1 in
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def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, $sp, $rhs", []>,
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T1Encoding<{1,0,1,0,1,?}> {
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// A6.2 & A8.6.8
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bits<3> dst;
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bits<8> rhs;
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let Inst{10-8} = dst;
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let Inst{7-0} = rhs;
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}
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// ADD sp, sp, #<imm7>
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, $rhs", []>,
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"add\t$dst, $rhs", []>,
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T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
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T1Misc<{0,0,0,0,0,?,?}> {
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// A6.2.5 & A8.6.8
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bits<7> rhs;
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let Inst{6-0} = rhs;
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}
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// SUB sp, sp, #imm7
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// SUB sp, sp, #<imm7>
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// FIXME: The encoding and the ASM string don't match up.
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def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
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"sub\t$dst, $rhs", []>,
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"sub\t$dst, $rhs", []>,
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T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
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T1Misc<{0,0,0,0,1,?,?}> {
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// A6.2.5 & A8.6.214
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bits<7> rhs;
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let Inst{6-0} = rhs;
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}
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// ADD rm, sp
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// ADD <Rm>, sp
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def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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"add\t$dst, $rhs", []>,
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"add\t$dst, $rhs", []>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}> {
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let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
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// A8.6.9 Encoding T1
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bits<4> dst;
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let Inst{7} = dst{3};
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let Inst{6-3} = 0b1101;
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let Inst{2-0} = dst{2-0};
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}
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}
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// ADD sp, rm
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// ADD sp, <Rm>
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def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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"add\t$dst, $rhs", []>,
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"add\t$dst, $rhs", []>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}> {
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// A8.6.9 Encoding T2
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// A8.6.9 Encoding T2
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bits<4> dst;
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let Inst{7} = 1;
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let Inst{7} = 1;
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let Inst{6-3} = dst;
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let Inst{2-0} = 0b101;
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let Inst{2-0} = 0b101;
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}
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}
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