6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-14 11:32:34 +00:00
Code Issues Projects Releases Wiki Activity

Wrap long lines

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-08-05 17:22:47 +00:00
parent 77327b8520
commit 0ae6dc9c21
1 changed files with 6 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/X86/X86InstrAVX512.td
View File

@ -4466,18 +4466,20 @@ multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, i8imm:$src3),
!strconcat(OpcodeStr,
" \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
" \t{$src3, $src2, $src1, $dst|"
"$dst, $src1, $src2, $src3}"),
[]>, EVEX_4V;
let mayLoad = 1 in
def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, x86memop:$src2, i8imm:$src3),
!strconcat(OpcodeStr,
" \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
" \t{$src3, $src2, $src1, $dst|"
"$dst, $src1, $src2, $src3}"),
[]>, EVEX_4V;
}
defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
EVEX_V512, EVEX_CD8<32, CD8VF>;
defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),