6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-07-26 05:25:47 +00:00
Code Issues Projects Releases Wiki Activity

Re-apply r135319 with a fix for the constant island pass.

Browse Source 
Original Log: Get rid of the separate opcodes for the Darwin versions of tBL, tBLXi, and tBLXr, using pseudo-instructions to lower to the single final opcode.  Update the ARM disassembler for this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135414 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-07-18 18:50:52 +00:00
parent fc47933db5
commit 0af0dc8ac6
4 changed files with 30 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@@ -479,7 +479,7 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
// tBX: Rm
// tBX_RET: 0 operand
// tBX_RET_vararg: Rm
// tBLXr_r9: Rm
// tBLXr: Rm
// tBRIND: Rm
static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
@@ -489,8 +489,8 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
return true;
// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
if (Opcode == ARM::tBLXr_r9) {
if (Opcode==ARM::tBLXr || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
if (Opcode == ARM::tBLXr) {
// Handling the two predicate operands before the reg operand.
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
return false;
@@ -1729,7 +1729,7 @@ static inline bool t2MiscCtrlInstr(uint32_t insn) {
// Branches: t2TPsoft -> no operand
//
// A8.6.23 BL, BLX (immediate)
// Branches (defined in ARMInstrThumb.td): tBLr9, tBLXi_r9 -> imm operand
// Branches (defined in ARMInstrThumb.td): tBL, tBLXi -> imm operand
//
// A8.6.26
// t2BXJ -> Rn
@@ -1844,7 +1844,7 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
}
// Some instructions have predicate operands first before the immediate.
if (Opcode == ARM::tBLXi_r9 || Opcode == ARM::tBLr9) {
if (Opcode == ARM::tBLXi || Opcode == ARM::tBL) {
// Handling the two predicate operands before the imm operand.
if (B->DoPredicateOperands(MI, Opcode, insn, NumOps))
NumOpsAdded += 2;
@@ -1867,10 +1867,10 @@ static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
case ARM::t2Bcc:
Offset = decodeImm32_B_EncodingT3(insn);
break;
case ARM::tBLr9:
case ARM::tBL:
Offset = decodeImm32_BL(insn);
break;
case ARM::tBLXi_r9:
case ARM::tBLXi:
Offset = decodeImm32_BLX(insn);
break;
}