From 0b2f9a266d6cee1cc62e7a22f725ac1bc09c50d3 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 1 Dec 2014 15:52:46 +0000 Subject: [PATCH] R600/SI: Various instruction format bit test cleanups - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223038 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/SIDefines.h | 30 ++++++++---- lib/Target/R600/SIInstrFormats.td | 58 +++++++++++++++++----- lib/Target/R600/SIInstrInfo.cpp | 52 -------------------- lib/Target/R600/SIInstrInfo.h | 80 ++++++++++++++++++++++++++----- lib/Target/R600/SIInstrInfo.td | 8 ---- 5 files changed, 134 insertions(+), 94 deletions(-) diff --git a/lib/Target/R600/SIDefines.h b/lib/Target/R600/SIDefines.h index 2e7dab6cb56..bc44e403f10 100644 --- a/lib/Target/R600/SIDefines.h +++ b/lib/Target/R600/SIDefines.h @@ -14,16 +14,26 @@ namespace SIInstrFlags { // This needs to be kept in sync with the field bits in InstSI. enum { - MIMG = 1 << 3, - SMRD = 1 << 4, - VOP1 = 1 << 5, - VOP2 = 1 << 6, - VOP3 = 1 << 7, - VOPC = 1 << 8, - SALU = 1 << 9, - MUBUF = 1 << 10, - MTBUF = 1 << 11, - FLAT = 1 << 12 + SALU = 1 << 3, + VALU = 1 << 4, + + SOP1 = 1 << 5, + SOP2 = 1 << 6, + SOPC = 1 << 7, + SOPK = 1 << 8, + SOPP = 1 << 9, + + VOP1 = 1 << 10, + VOP2 = 1 << 11, + VOP3 = 1 << 12, + VOPC = 1 << 13, + + MUBUF = 1 << 14, + MTBUF = 1 << 15, + SMRD = 1 << 16, + DS = 1 << 17, + MIMG = 1 << 18, + FLAT = 1 << 19 }; } diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index 0fbce35cdbf..3301a82bd09 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -17,31 +17,53 @@ class InstSI pattern> : field bits<1> VM_CNT = 0; field bits<1> EXP_CNT = 0; field bits<1> LGKM_CNT = 0; - field bits<1> MIMG = 0; - field bits<1> SMRD = 0; + + field bits<1> SALU = 0; + field bits<1> VALU = 0; + + field bits<1> SOP1 = 0; + field bits<1> SOP2 = 0; + field bits<1> SOPC = 0; + field bits<1> SOPK = 0; + field bits<1> SOPP = 0; + field bits<1> VOP1 = 0; field bits<1> VOP2 = 0; field bits<1> VOP3 = 0; field bits<1> VOPC = 0; - field bits<1> SALU = 0; + field bits<1> MUBUF = 0; field bits<1> MTBUF = 0; + field bits<1> SMRD = 0; + field bits<1> DS = 0; + field bits<1> MIMG = 0; field bits<1> FLAT = 0; // These need to be kept in sync with the enum in SIInstrFlags. let TSFlags{0} = VM_CNT; let TSFlags{1} = EXP_CNT; let TSFlags{2} = LGKM_CNT; - let TSFlags{3} = MIMG; - let TSFlags{4} = SMRD; - let TSFlags{5} = VOP1; - let TSFlags{6} = VOP2; - let TSFlags{7} = VOP3; - let TSFlags{8} = VOPC; - let TSFlags{9} = SALU; - let TSFlags{10} = MUBUF; - let TSFlags{11} = MTBUF; - let TSFlags{12} = FLAT; + + let TSFlags{3} = SALU; + let TSFlags{4} = VALU; + + let TSFlags{5} = SOP1; + let TSFlags{6} = SOP2; + let TSFlags{7} = SOPC; + let TSFlags{8} = SOPK; + let TSFlags{9} = SOPP; + + let TSFlags{10} = VOP1; + let TSFlags{11} = VOP2; + let TSFlags{12} = VOP3; + let TSFlags{13} = VOPC; + + let TSFlags{14} = MUBUF; + let TSFlags{15} = MTBUF; + let TSFlags{16} = SMRD; + let TSFlags{17} = DS; + let TSFlags{18} = MIMG; + let TSFlags{19} = FLAT; // Most instructions require adjustments after selection to satisfy // operand requirements. @@ -67,6 +89,7 @@ class VOP1Common pattern> : let hasSideEffects = 0; let UseNamedOperandTable = 1; let VOP1 = 1; + let VALU = 1; } class VOP3Common pattern> : @@ -83,6 +106,7 @@ class VOP3Common pattern> : let AddedComplexity = -1000; let VOP3 = 1; + let VALU = 1; int Size = 8; let Uses = [EXEC]; @@ -168,6 +192,7 @@ class SOP1 op, dag outs, dag ins, string asm, list pattern> : let mayStore = 0; let hasSideEffects = 0; let SALU = 1; + let SOP1 = 1; } class SOP2 op, dag outs, dag ins, string asm, list pattern> : @@ -177,6 +202,7 @@ class SOP2 op, dag outs, dag ins, string asm, list pattern> : let mayStore = 0; let hasSideEffects = 0; let SALU = 1; + let SOP2 = 1; let UseNamedOperandTable = 1; } @@ -189,6 +215,7 @@ class SOPC op, dag outs, dag ins, string asm, list pattern> : let mayStore = 0; let hasSideEffects = 0; let SALU = 1; + let SOPC = 1; let UseNamedOperandTable = 1; } @@ -200,6 +227,7 @@ class SOPK op, dag outs, dag ins, string asm, list pattern> : let mayStore = 0; let hasSideEffects = 0; let SALU = 1; + let SOPK = 1; let UseNamedOperandTable = 1; } @@ -212,6 +240,7 @@ class SOPP op, dag ins, string asm, list pattern = []> : let hasSideEffects = 0; let isCodeGenOnly = 0; let SALU = 1; + let SOPP = 1; let UseNamedOperandTable = 1; } @@ -507,6 +536,7 @@ class VOP2 op, dag outs, dag ins, string asm, list pattern> : let hasSideEffects = 0; let UseNamedOperandTable = 1; let VOP2 = 1; + let VALU = 1; } class VOP3 op, dag outs, dag ins, string asm, list pattern> : @@ -524,6 +554,7 @@ class VOPC op, dag ins, string asm, list pattern> : let hasSideEffects = 0; let UseNamedOperandTable = 1; let VOPC = 1; + let VALU = 1; } class VINTRP op, dag outs, dag ins, string asm, list pattern> : @@ -545,6 +576,7 @@ class DS op, dag outs, dag ins, string asm, list pattern> : InstSI , DSe { let LGKM_CNT = 1; + let DS = 1; let UseNamedOperandTable = 1; let DisableEncoding = "$m0"; } diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index 1a0010c03dc..21aadea1e93 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -895,58 +895,6 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa, return false; } -namespace llvm { -namespace AMDGPU { -// Helper function generated by tablegen. We are wrapping this with -// an SIInstrInfo function that returns bool rather than int. -int isDS(uint16_t Opcode); -} -} - -bool SIInstrInfo::isDS(uint16_t Opcode) const { - return ::AMDGPU::isDS(Opcode) != -1; -} - -bool SIInstrInfo::isMIMG(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::MIMG; -} - -bool SIInstrInfo::isSMRD(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::SMRD; -} - -bool SIInstrInfo::isMUBUF(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::MUBUF; -} - -bool SIInstrInfo::isMTBUF(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::MTBUF; -} - -bool SIInstrInfo::isFLAT(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::FLAT; -} - -bool SIInstrInfo::isVOP1(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::VOP1; -} - -bool SIInstrInfo::isVOP2(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::VOP2; -} - -bool SIInstrInfo::isVOP3(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::VOP3; -} - -bool SIInstrInfo::isVOPC(uint16_t Opcode) const { - return get(Opcode).TSFlags & SIInstrFlags::VOPC; -} - -bool SIInstrInfo::isSALUInstr(const MachineInstr &MI) const { - return get(MI.getOpcode()).TSFlags & SIInstrFlags::SALU; -} - bool SIInstrInfo::isInlineConstant(const APInt &Imm) const { int32_t Val = Imm.getSExtValue(); if (Val >= -16 && Val <= 64) diff --git a/lib/Target/R600/SIInstrInfo.h b/lib/Target/R600/SIInstrInfo.h index 3bdbc9b5498..5295606c548 100644 --- a/lib/Target/R600/SIInstrInfo.h +++ b/lib/Target/R600/SIInstrInfo.h @@ -17,6 +17,7 @@ #define LLVM_LIB_TARGET_R600_SIINSTRINFO_H #include "AMDGPUInstrInfo.h" +#include "SIDefines.h" #include "SIRegisterInfo.h" namespace llvm { @@ -128,16 +129,74 @@ public: bool isMov(unsigned Opcode) const override; bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override; - bool isDS(uint16_t Opcode) const; - bool isMIMG(uint16_t Opcode) const; - bool isSMRD(uint16_t Opcode) const; - bool isMUBUF(uint16_t Opcode) const; - bool isMTBUF(uint16_t Opcode) const; - bool isFLAT(uint16_t Opcode) const; - bool isVOP1(uint16_t Opcode) const; - bool isVOP2(uint16_t Opcode) const; - bool isVOP3(uint16_t Opcode) const; - bool isVOPC(uint16_t Opcode) const; + + bool isSALU(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SALU; + } + + bool isVALU(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::VALU; + } + + bool isSOP1(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SOP1; + } + + bool isSOP2(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SOP2; + } + + bool isSOPC(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SOPC; + } + + bool isSOPK(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SOPK; + } + + bool isSOPP(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SOPP; + } + + bool isVOP1(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::VOP1; + } + + bool isVOP2(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::VOP2; + } + + bool isVOP3(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::VOP3; + } + + bool isVOPC(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::VOPC; + } + + bool isMUBUF(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::MUBUF; + } + + bool isMTBUF(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::MTBUF; + } + + bool isSMRD(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::SMRD; + } + + bool isDS(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::DS; + } + + bool isMIMG(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::MIMG; + } + + bool isFLAT(uint16_t Opcode) const { + return get(Opcode).TSFlags & SIInstrFlags::FLAT; + } bool isInlineConstant(const APInt &Imm) const; bool isInlineConstant(const MachineOperand &MO) const; @@ -168,7 +227,6 @@ public: bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const override; - bool isSALUInstr(const MachineInstr &MI) const; static unsigned getVALUOp(const MachineInstr &MI); bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td index 392c272a863..cdbc22e0ead 100644 --- a/lib/Target/R600/SIInstrInfo.td +++ b/lib/Target/R600/SIInstrInfo.td @@ -1497,14 +1497,6 @@ def getCommuteOrig : InstrMapping { let ValueCols = [["1"]]; } -def isDS : InstrMapping { - let FilterClass = "DS"; - let RowFields = ["Inst"]; - let ColFields = ["Size"]; - let KeyCol = ["8"]; - let ValueCols = [["8"]]; -} - def getMCOpcode : InstrMapping { let FilterClass = "SIMCInstr"; let RowFields = ["PseudoInstr"];