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Fix CellSPU vector shuffles, again.

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Some cases of lowering to rotate were miscompiled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kalle Raiskila
2010-09-08 11:53:38 +00:00
parent c8ae35a8e8
commit 0b4ab0cfe0
2 changed files with 33 additions and 7 deletions
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26
test/CodeGen/CellSPU/shuffles.ll
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@@ -39,3 +39,29 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
ret <4 x float> %rv
}
define <2 x i32> @test_v2i32(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 4
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
ret <2 x i32> %rv
}
define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 8
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 2,i32 3,i32 0, i32 1>
ret <4 x i32> %rv
}
define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
{
;CHECK: rotqbyi $3, $3, 4
;CHECK: bi $lr
%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
<4 x i32> <i32 1,i32 2,i32 3, i32 0>
ret <4 x i32> %rv
}