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Fix CellSPU vector shuffles, again.
Some cases of lowering to rotate were miscompiled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113355 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1735,9 +1735,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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unsigned CurrElt = 0;
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unsigned MaxElts = VecVT.getVectorNumElements();
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unsigned PrevElt = 0;
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unsigned V0Elt = 0;
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bool monotonic = true;
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bool rotate = true;
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int rotamt;
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EVT maskVT; // which of the c?d instructions to use
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if (EltVT == MVT::i8) {
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@ -1781,14 +1781,13 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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if (PrevElt > 0 && SrcElt < MaxElts) {
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if ((PrevElt == SrcElt - 1)
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|| (PrevElt == MaxElts - 1 && SrcElt == 0)) {
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rotamt = SrcElt-i;
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PrevElt = SrcElt;
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if (SrcElt == 0)
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V0Elt = i;
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} else {
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rotate = false;
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}
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} else if (i == 0) {
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// First time through, need to keep track of previous element
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} else if (i == 0 || (PrevElt==0 && SrcElt==1)) {
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// First time or after a "wrap around"
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PrevElt = SrcElt;
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} else {
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// This isn't a rotation, takes elements from vector 2
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@ -1813,8 +1812,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1,
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ShufMaskOp);
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} else if (rotate) {
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int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8;
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if (rotamt < 0)
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rotamt +=MaxElts;
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rotamt *= EltVT.getSizeInBits()/8;
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return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(),
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V1, DAG.getConstant(rotamt, MVT::i16));
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} else {
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@ -39,3 +39,29 @@ define <4 x float> @test_insert_1(<4 x float> %vparam, float %eltparam) {
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ret <4 x float> %rv
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}
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define <2 x i32> @test_v2i32(<4 x i32>%vec)
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{
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;CHECK: rotqbyi $3, $3, 4
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;CHECK: bi $lr
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef, <2 x i32><i32 1,i32 2>
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ret <2 x i32> %rv
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}
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define <4 x i32> @test_v4i32_rot8(<4 x i32>%vec)
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{
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;CHECK: rotqbyi $3, $3, 8
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;CHECK: bi $lr
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
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<4 x i32> <i32 2,i32 3,i32 0, i32 1>
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ret <4 x i32> %rv
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}
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define <4 x i32> @test_v4i32_rot4(<4 x i32>%vec)
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{
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;CHECK: rotqbyi $3, $3, 4
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;CHECK: bi $lr
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%rv = shufflevector <4 x i32> %vec, <4 x i32> undef,
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<4 x i32> <i32 1,i32 2,i32 3, i32 0>
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ret <4 x i32> %rv
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}
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