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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-26 23:24:34 +00:00
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29907 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -457,8 +457,9 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
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AddToISelQueue(Tmp3);
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AddToISelQueue(Op1);
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SH &= 31;
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return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp3, Op1,
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getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
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SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
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getI32Imm(ME) };
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return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
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}
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}
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return 0;
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@ -809,10 +810,11 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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AddToISelQueue(Op);
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switch (CC) {
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default: break;
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case ISD::SETEQ:
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case ISD::SETEQ: {
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Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27),
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getI32Imm(5), getI32Imm(31));
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SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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case ISD::SETNE: {
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SDOperand AD =
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SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
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@ -820,15 +822,16 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
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AD.getValue(1));
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}
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case ISD::SETLT:
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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case ISD::SETLT: {
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SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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case ISD::SETGT: {
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SDOperand T =
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SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
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T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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}
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} else if (Imm == ~0U) { // setcc op, -1
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@ -855,16 +858,16 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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getI32Imm(1)), 0);
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SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
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Op), 0);
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1),
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getI32Imm(31), getI32Imm(31));
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SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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case ISD::SETGT:
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Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op,
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getI32Imm(1), getI32Imm(31),
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getI32Imm(31)), 0);
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case ISD::SETGT: {
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SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
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Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
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return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
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getI32Imm(1));
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}
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}
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}
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}
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@ -886,15 +889,13 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
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else
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IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
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SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
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getI32Imm(31), getI32Imm(31) };
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if (!Inv) {
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm((32-(3-Idx)) & 31),
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getI32Imm(31), getI32Imm(31));
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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} else {
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SDOperand Tmp =
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SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR,
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getI32Imm((32-(3-Idx)) & 31),
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getI32Imm(31),getI32Imm(31)), 0);
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SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
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return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
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}
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}
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@ -990,9 +991,8 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
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isRunOfOnes(Imm, MB, ME);
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SH = 0;
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}
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val,
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getI32Imm(SH), getI32Imm(MB),
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getI32Imm(ME));
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SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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// ISD::OR doesn't get all the bitfield insertion fun.
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// (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
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@ -1004,10 +1004,10 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
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if (isRunOfOnes(Imm, MB, ME)) {
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AddToISelQueue(N->getOperand(0).getOperand(0));
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AddToISelQueue(N->getOperand(0).getOperand(1));
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return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32,
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N->getOperand(0).getOperand(0),
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N->getOperand(0).getOperand(1),
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getI32Imm(0), getI32Imm(MB),getI32Imm(ME));
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SDOperand Ops[] = { N->getOperand(0).getOperand(0),
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N->getOperand(0).getOperand(1),
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getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
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return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
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}
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}
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@ -1026,10 +1026,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
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if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
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isRotateAndMask(N, Imm, true, SH, MB, ME)) {
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AddToISelQueue(N->getOperand(0).getOperand(0));
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
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N->getOperand(0).getOperand(0),
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getI32Imm(SH), getI32Imm(MB),
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getI32Imm(ME));
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SDOperand Ops[] = { N->getOperand(0).getOperand(0),
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getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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// Other cases are autogenerated.
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@ -1040,10 +1039,9 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
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if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
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isRotateAndMask(N, Imm, true, SH, MB, ME)) {
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AddToISelQueue(N->getOperand(0).getOperand(0));
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32,
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N->getOperand(0).getOperand(0),
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getI32Imm(SH), getI32Imm(MB),
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getI32Imm(ME));
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SDOperand Ops[] = { N->getOperand(0).getOperand(0),
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getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
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return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
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}
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// Other cases are autogenerated.
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@ -1087,17 +1085,17 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
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AddToISelQueue(N->getOperand(2));
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AddToISelQueue(N->getOperand(3));
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return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg,
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N->getOperand(2), N->getOperand(3),
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getI32Imm(BROpc));
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SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
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getI32Imm(BROpc) };
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return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
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}
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case ISD::BR_CC: {
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AddToISelQueue(N->getOperand(0));
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ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
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SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
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return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other,
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CondCode, getI32Imm(getBCCForSetCC(CC)),
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N->getOperand(4), N->getOperand(0));
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SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)),
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N->getOperand(4), N->getOperand(0) };
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return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
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}
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case ISD::BRIND: {
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// FIXME: Should custom lower this.
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