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Use PMULDQ for v2i64 multiplies when SSE4.1 is available. And add
load-folding table entries for PMULDQ and PMULLD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51489 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -700,6 +700,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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if (Subtarget->hasSSE41()) {
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// FIXME: Do we need to handle scalar-to-vector here?
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setOperationAction(ISD::MUL, MVT::v4i32, Legal);
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setOperationAction(ISD::MUL, MVT::v2i64, Legal);
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// i8 and i16 vectors are custom , because the source register and source
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// source memory operand types are not the same width. f32 vectors are
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@ -569,8 +569,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
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{ X86::PMAXUBrr, X86::PMAXUBrm },
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{ X86::PMINSWrr, X86::PMINSWrm },
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{ X86::PMINUBrr, X86::PMINUBrm },
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{ X86::PMULDQrr, X86::PMULDQrm },
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{ X86::PMULDQrr_int, X86::PMULDQrm_int },
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{ X86::PMULHUWrr, X86::PMULHUWrm },
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{ X86::PMULHWrr, X86::PMULHWrm },
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{ X86::PMULLDrr, X86::PMULLDrm },
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{ X86::PMULLDrr_int, X86::PMULLDrm_int },
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{ X86::PMULLWrr, X86::PMULLWrm },
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{ X86::PMULUDQrr, X86::PMULUDQrm },
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{ X86::PORrr, X86::PORrm },
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@ -3242,18 +3242,17 @@ defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
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int_x86_sse41_pmaxud, 1>;
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defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
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int_x86_sse41_pmaxuw, 1>;
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defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq",
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int_x86_sse41_pmuldq, 1>;
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/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
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let Constraints = "$src1 = $dst" in {
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multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, SDNode OpNode,
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Intrinsic IntId128, bit Commutable = 0> {
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multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
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SDNode OpNode, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode (v4i32 VR128:$src1),
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[(set VR128:$dst, (OpNode (OpVT VR128:$src1),
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VR128:$src2))]>, OpSize {
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let isCommutable = Commutable;
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}
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@ -3277,8 +3276,10 @@ let Constraints = "$src1 = $dst" in {
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OpSize;
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}
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}
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defm PMULLD : SS41I_binop_patint<0x40, "pmulld", mul,
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defm PMULLD : SS41I_binop_patint<0x40, "pmulld", v4i32, mul,
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int_x86_sse41_pmulld, 1>;
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defm PMULDQ : SS41I_binop_patint<0x28, "pmuldq", v2i64, mul,
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int_x86_sse41_pmuldq, 1>;
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/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
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32
test/CodeGen/X86/pmul.ll
Normal file
32
test/CodeGen/X86/pmul.ll
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@ -0,0 +1,32 @@
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; RUN: llvm-as < %s | llc -march=x86 -mattr=sse41 > %t
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; RUN: grep pmul %t | count 6
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; RUN: grep mov %t | count 8
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define <4 x i32> @a(<4 x i32> %i) nounwind {
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%A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 >
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ret <4 x i32> %A
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}
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define <2 x i64> @b(<2 x i64> %i) nounwind {
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%A = mul <2 x i64> %i, < i64 117, i64 117 >
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ret <2 x i64> %A
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}
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define <4 x i32> @c(<4 x i32> %i, <4 x i32> %j) nounwind {
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%A = mul <4 x i32> %i, %j
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ret <4 x i32> %A
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}
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define <2 x i64> @d(<2 x i64> %i, <2 x i64> %j) nounwind {
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%A = mul <2 x i64> %i, %j
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ret <2 x i64> %A
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}
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; Use a call to force spills.
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declare void @foo()
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define <4 x i32> @e(<4 x i32> %i, <4 x i32> %j) nounwind {
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call void @foo()
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%A = mul <4 x i32> %i, %j
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ret <4 x i32> %A
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}
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define <2 x i64> @f(<2 x i64> %i, <2 x i64> %j) nounwind {
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call void @foo()
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%A = mul <2 x i64> %i, %j
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ret <2 x i64> %A
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}
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