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[mips] Use ADDu instead of OR to copy general purpose registers. Also, delete
the InstAlias pattern which maps "move" to OR to resolve ambiguity in MatchTable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186855 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -333,9 +333,6 @@ def : MipsPat<(i64 (ExtractLOHI ACRegs128:$ac, imm:$lohi_idx)),
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def : InstAlias<"move $dst, $src",
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(DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"move $dst, $src",
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(OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
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Requires<[HasMips64]>;
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def : InstAlias<"and $rs, $rt, $imm",
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(DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
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1>,
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@ -1099,9 +1099,6 @@ def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
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def : InstAlias<"move $dst, $src",
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(ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
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Requires<[NotMips64]>;
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def : InstAlias<"move $dst, $src",
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(OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
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Requires<[NotMips64]>;
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def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
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def : InstAlias<"addu $rs, $rt, $imm",
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(ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
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@ -96,7 +96,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
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if (Mips::CPURegsRegClass.contains(SrcReg))
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Opc = Mips::OR, ZeroReg = Mips::ZERO;
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Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
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else if (Mips::CCRRegClass.contains(SrcReg))
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Opc = Mips::CFC1;
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else if (Mips::FGR32RegClass.contains(SrcReg))
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@ -143,7 +143,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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Opc = Mips::FMOV_D64;
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else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
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if (Mips::CPU64RegsRegClass.contains(SrcReg))
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Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
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Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
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else if (Mips::HIRegs64RegClass.contains(SrcReg))
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Opc = Mips::MFHI64, SrcReg = 0;
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else if (Mips::LORegs64RegClass.contains(SrcReg))
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@ -511,7 +511,6 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
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// indirect jump to TargetReg
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const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
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unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
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unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR;
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unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
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unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
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unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
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@ -520,13 +519,13 @@ void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
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unsigned OffsetReg = I->getOperand(0).getReg();
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unsigned TargetReg = I->getOperand(1).getReg();
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// or $ra, $v0, $zero
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// addu $ra, $v0, $zero
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// addu $sp, $sp, $v1
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// jr $ra
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if (TM.getRelocationModel() == Reloc::PIC_)
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), T9)
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
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.addReg(TargetReg).addReg(ZERO);
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
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.addReg(TargetReg).addReg(ZERO);
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BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
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.addReg(SP).addReg(OffsetReg);
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@ -13,6 +13,7 @@
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# CHECK: ins $19, $9, 6, 7 # encoding: [0x84,0x61,0x33,0x7d]
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# CHECK: nor $9, $6, $7 # encoding: [0x27,0x48,0xc7,0x00]
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# CHECK: or $3, $3, $5 # encoding: [0x25,0x18,0x65,0x00]
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# CHECK: or $3, $2, $zero # encoding: [0x25,0x18,0x40,0x00]
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# CHECK: ori $4, $5, 17767 # encoding: [0x67,0x45,0xa4,0x34]
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# CHECK: ori $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x34]
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# CHECK: ori $11, $11, 128 # encoding: [0x80,0x00,0x6b,0x35]
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@ -44,6 +45,7 @@
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ins $19, $9, 6,7
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nor $9, $6, $7
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or $3, $3, $5
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or $3, $2, $zero
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or $4, $5, 17767
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ori $9, $6, 17767
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ori $11, 128
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