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Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson 2009-10-08 22:27:33 +00:00
parent c6f520be0d
commit 0bf7d998b4
4 changed files with 146 additions and 20 deletions
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73
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -1577,18 +1577,73 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue MemAddr, MemUpdate, MemOpc;
if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
return NULL;
if (VT.is64BitVector()) {
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld3lane type");
case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), N->getOperand(6), Chain };
return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
}
// Quad registers are handled by extracting subregs, doing the load,
// and then inserting the results as subregs.
EVT RegVT;
unsigned Opc2 = 0;
switch (VT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("unhandled vld3lane type");
case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
default: llvm_unreachable("unhandled vld2lane type");
case MVT::v8i16:
Opc = ARM::VLD3LNq16a;
Opc2 = ARM::VLD3LNq16b;
RegVT = MVT::v4i16;
break;
case MVT::v4f32:
Opc = ARM::VLD3LNq32a;
Opc2 = ARM::VLD3LNq32b;
RegVT = MVT::v2f32;
break;
case MVT::v4i32:
Opc = ARM::VLD3LNq32a;
Opc2 = ARM::VLD3LNq32b;
RegVT = MVT::v2i32;
break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
N->getOperand(3), N->getOperand(4),
N->getOperand(5), N->getOperand(6), Chain };
return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
unsigned NumElts = RegVT.getVectorNumElements();
int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(3));
SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(4));
SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
N->getOperand(5));
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
getI32Imm(Lane % NumElts), Chain };
SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
dl, RegVT, RegVT, RegVT,
MVT::Other, Ops, 8);
SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
N->getOperand(3),
SDValue(VLdLn, 0));
SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
N->getOperand(4),
SDValue(VLdLn, 1));
SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
N->getOperand(5),
SDValue(VLdLn, 2));
Chain = SDValue(VLdLn, 3);
ReplaceUses(SDValue(N, 0), Q0);
ReplaceUses(SDValue(N, 1), Q1);
ReplaceUses(SDValue(N, 2), Q2);
ReplaceUses(SDValue(N, 3), Chain);
return NULL;
}
case Intrinsic::arm_neon_vld4lane: {

16
lib/Target/ARM/ARMInstrNEON.td
View File

@ -286,7 +286,7 @@ def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
// VLD3LN : Vector Load (single 3-element structure to one lane)
class VLD3LND<bits<4> op11_8, string OpcodeStr>
class VLD3LN<bits<4> op11_8, string OpcodeStr>
: NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
nohash_imm:$lane), IIC_VLD3,
@ -294,9 +294,17 @@ class VLD3LND<bits<4> op11_8, string OpcodeStr>
"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
def VLD3LNd8 : VLD3LND<0b0010, "vld3.8">;
def VLD3LNd16 : VLD3LND<0b0110, "vld3.16">;
def VLD3LNd32 : VLD3LND<0b1010, "vld3.32">;
def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">;
def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">;
def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">;
// vld3 to double-spaced even registers.
def VLD3LNq16a: VLD3LN<0b0101, "vld3.16">;
def VLD3LNq32a: VLD3LN<0b1001, "vld3.32">;
// vld3 to double-spaced odd registers.
def VLD3LNq16b: VLD3LN<0b0101, "vld3.16">;
def VLD3LNq32b: VLD3LN<0b1001, "vld3.32">;
// VLD4LN : Vector Load (single 4-element structure to one lane)
class VLD4LND<bits<4> op11_8, string OpcodeStr>

30
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@ -57,6 +57,13 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
NumRegs = 2;
return true;
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
FirstOpnd = 0;
NumRegs = 4;
return true;
case ARM::VLD2LNq16a:
case ARM::VLD2LNq32a:
FirstOpnd = 0;
@ -73,13 +80,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
Stride = 2;
return true;
case ARM::VLD2q8:
case ARM::VLD2q16:
case ARM::VLD2q32:
FirstOpnd = 0;
NumRegs = 4;
return true;
case ARM::VLD3d8:
case ARM::VLD3d16:
case ARM::VLD3d32:
@ -109,6 +109,22 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
Stride = 2;
return true;
case ARM::VLD3LNq16a:
case ARM::VLD3LNq32a:
FirstOpnd = 0;
NumRegs = 3;
Offset = 0;
Stride = 2;
return true;
case ARM::VLD3LNq16b:
case ARM::VLD3LNq32b:
FirstOpnd = 0;
NumRegs = 3;
Offset = 1;
Stride = 2;
return true;
case ARM::VLD4d8:
case ARM::VLD4d16:
case ARM::VLD4d32:

47
test/CodeGen/ARM/vldlane.ll
View File

@ -100,6 +100,10 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo
%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
;CHECK: vld3lanei8:
;CHECK: vld3.8
@ -152,11 +156,54 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
ret <2 x float> %tmp7
}
define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
;CHECK: vld3laneQi16:
;CHECK: vld3.16
%tmp1 = load <8 x i16>* %B
%tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
%tmp6 = add <8 x i16> %tmp3, %tmp4
%tmp7 = add <8 x i16> %tmp5, %tmp6
ret <8 x i16> %tmp7
}
define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
;CHECK: vld3laneQi32:
;CHECK: vld3.32
%tmp1 = load <4 x i32>* %B
%tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3)
%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
%tmp6 = add <4 x i32> %tmp3, %tmp4
%tmp7 = add <4 x i32> %tmp5, %tmp6
ret <4 x i32> %tmp7
}
define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
;CHECK: vld3laneQf:
;CHECK: vld3.32
%tmp1 = load <4 x float>* %B
%tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
%tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
%tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
%tmp6 = add <4 x float> %tmp3, %tmp4
%tmp7 = add <4 x float> %tmp5, %tmp6
ret <4 x float> %tmp7
}
declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind readonly
declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind readonly
declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind readonly
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }