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Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83585 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1577,6 +1577,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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SDValue MemAddr, MemUpdate, MemOpc;
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if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
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return NULL;
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if (VT.is64BitVector()) {
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld3lane type");
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case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
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@ -1590,6 +1591,60 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
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N->getOperand(5), N->getOperand(6), Chain };
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return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
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}
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// Quad registers are handled by extracting subregs, doing the load,
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// and then inserting the results as subregs.
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EVT RegVT;
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unsigned Opc2 = 0;
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switch (VT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("unhandled vld2lane type");
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case MVT::v8i16:
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Opc = ARM::VLD3LNq16a;
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Opc2 = ARM::VLD3LNq16b;
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RegVT = MVT::v4i16;
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break;
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case MVT::v4f32:
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Opc = ARM::VLD3LNq32a;
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Opc2 = ARM::VLD3LNq32b;
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RegVT = MVT::v2f32;
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break;
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case MVT::v4i32:
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Opc = ARM::VLD3LNq32a;
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Opc2 = ARM::VLD3LNq32b;
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RegVT = MVT::v2i32;
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break;
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}
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SDValue Chain = N->getOperand(0);
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unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
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unsigned NumElts = RegVT.getVectorNumElements();
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int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
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SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
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N->getOperand(3));
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SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
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N->getOperand(4));
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SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
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N->getOperand(5));
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const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
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getI32Imm(Lane % NumElts), Chain };
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SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
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dl, RegVT, RegVT, RegVT,
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MVT::Other, Ops, 8);
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SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
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N->getOperand(3),
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SDValue(VLdLn, 0));
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SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
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N->getOperand(4),
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SDValue(VLdLn, 1));
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SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
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N->getOperand(5),
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SDValue(VLdLn, 2));
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Chain = SDValue(VLdLn, 3);
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ReplaceUses(SDValue(N, 0), Q0);
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ReplaceUses(SDValue(N, 1), Q1);
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ReplaceUses(SDValue(N, 2), Q2);
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ReplaceUses(SDValue(N, 3), Chain);
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return NULL;
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}
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case Intrinsic::arm_neon_vld4lane: {
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SDValue MemAddr, MemUpdate, MemOpc;
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@ -286,7 +286,7 @@ def VLD2LNq16b: VLD2LN<0b0101, "vld2.16">;
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def VLD2LNq32b: VLD2LN<0b1001, "vld2.32">;
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// VLD3LN : Vector Load (single 3-element structure to one lane)
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class VLD3LND<bits<4> op11_8, string OpcodeStr>
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class VLD3LN<bits<4> op11_8, string OpcodeStr>
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: NLdSt<1,0b10,op11_8,0b0000, (outs DPR:$dst1, DPR:$dst2, DPR:$dst3),
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(ins addrmode6:$addr, DPR:$src1, DPR:$src2, DPR:$src3,
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nohash_imm:$lane), IIC_VLD3,
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@ -294,9 +294,17 @@ class VLD3LND<bits<4> op11_8, string OpcodeStr>
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"\t\\{$dst1[$lane],$dst2[$lane],$dst3[$lane]\\}, $addr"),
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"$src1 = $dst1, $src2 = $dst2, $src3 = $dst3", []>;
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def VLD3LNd8 : VLD3LND<0b0010, "vld3.8">;
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def VLD3LNd16 : VLD3LND<0b0110, "vld3.16">;
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def VLD3LNd32 : VLD3LND<0b1010, "vld3.32">;
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def VLD3LNd8 : VLD3LN<0b0010, "vld3.8">;
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def VLD3LNd16 : VLD3LN<0b0110, "vld3.16">;
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def VLD3LNd32 : VLD3LN<0b1010, "vld3.32">;
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// vld3 to double-spaced even registers.
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def VLD3LNq16a: VLD3LN<0b0101, "vld3.16">;
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def VLD3LNq32a: VLD3LN<0b1001, "vld3.32">;
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// vld3 to double-spaced odd registers.
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def VLD3LNq16b: VLD3LN<0b0101, "vld3.16">;
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def VLD3LNq32b: VLD3LN<0b1001, "vld3.32">;
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// VLD4LN : Vector Load (single 4-element structure to one lane)
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class VLD4LND<bits<4> op11_8, string OpcodeStr>
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@ -57,6 +57,13 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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NumRegs = 2;
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return true;
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case ARM::VLD2q8:
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case ARM::VLD2q16:
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case ARM::VLD2q32:
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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case ARM::VLD2LNq16a:
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case ARM::VLD2LNq32a:
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FirstOpnd = 0;
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@ -73,13 +80,6 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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Stride = 2;
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return true;
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case ARM::VLD2q8:
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case ARM::VLD2q16:
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case ARM::VLD2q32:
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FirstOpnd = 0;
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NumRegs = 4;
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return true;
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case ARM::VLD3d8:
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case ARM::VLD3d16:
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case ARM::VLD3d32:
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@ -109,6 +109,22 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
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Stride = 2;
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return true;
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case ARM::VLD3LNq16a:
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case ARM::VLD3LNq32a:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 0;
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Stride = 2;
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return true;
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case ARM::VLD3LNq16b:
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case ARM::VLD3LNq32b:
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FirstOpnd = 0;
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NumRegs = 3;
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Offset = 1;
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Stride = 2;
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return true;
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case ARM::VLD4d8:
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case ARM::VLD4d16:
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case ARM::VLD4d32:
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@ -100,6 +100,10 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo
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%struct.__neon_int32x2x3_t = type { <2 x i32>, <2 x i32>, <2 x i32> }
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%struct.__neon_float32x2x3_t = type { <2 x float>, <2 x float>, <2 x float> }
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%struct.__neon_int16x8x3_t = type { <8 x i16>, <8 x i16>, <8 x i16> }
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%struct.__neon_int32x4x3_t = type { <4 x i32>, <4 x i32>, <4 x i32> }
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%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
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define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK: vld3lanei8:
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;CHECK: vld3.8
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@ -152,11 +156,54 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
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ret <2 x float> %tmp7
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}
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define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK: vld3laneQi16:
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;CHECK: vld3.16
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%tmp1 = load <8 x i16>* %B
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%tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i16* %A, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
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%tmp3 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int16x8x3_t %tmp2, 2
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%tmp6 = add <8 x i16> %tmp3, %tmp4
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%tmp7 = add <8 x i16> %tmp5, %tmp6
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ret <8 x i16> %tmp7
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}
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define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK: vld3laneQi32:
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;CHECK: vld3.32
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%tmp1 = load <4 x i32>* %B
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%tmp2 = call %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i32* %A, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 3)
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%tmp3 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_int32x4x3_t %tmp2, 2
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%tmp6 = add <4 x i32> %tmp3, %tmp4
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%tmp7 = add <4 x i32> %tmp5, %tmp6
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ret <4 x i32> %tmp7
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}
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define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
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;CHECK: vld3laneQf:
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;CHECK: vld3.32
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%tmp1 = load <4 x float>* %B
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%tmp2 = call %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(float* %A, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
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%tmp3 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 0
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%tmp4 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 1
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%tmp5 = extractvalue %struct.__neon_float32x4x3_t %tmp2, 2
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%tmp6 = add <4 x float> %tmp3, %tmp4
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%tmp7 = add <4 x float> %tmp5, %tmp6
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ret <4 x float> %tmp7
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}
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declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind readonly
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declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind readonly
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declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3lane.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind readonly
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declare %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3lane.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, i32) nounwind readonly
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declare %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind readonly
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declare %struct.__neon_int32x4x3_t @llvm.arm.neon.vld3lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind readonly
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declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, i32) nounwind readonly
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%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
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%struct.__neon_int16x4x4_t = type { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> }
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%struct.__neon_int32x2x4_t = type { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> }
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