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[SparcV9] For codegen generated library calls that return float, set inreg flag manually in LowerCall().

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This makes the sparc backend to generate Sparc64 ABI compliant code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198149 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-12-29 04:27:21 +00:00
parent 006e786b35
commit 0c67825459
2 changed files with 27 additions and 0 deletions
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6
lib/Target/Sparc/SparcISelLowering.cpp
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@ -1252,6 +1252,12 @@ SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI,
SmallVector<CCValAssign, 16> RVLocs;
CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(),
DAG.getTarget(), RVLocs, *DAG.getContext());
// Set inreg flag manually for codegen generated library calls that
// return float.
if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0)
CLI.Ins[0].Flags.setInReg();
RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64);
// Copy all of the result registers out of their specified physreg.

21
test/CodeGen/SPARC/64abi.ll
View File

@ -440,4 +440,25 @@ entry:
ret i64 %0
}
; CHECK-LABEL: test_call_libfunc
; CHECK: st %f1, [%fp+[[Offset0:[0-9]+]]]
; CHECK: fmovs %f3, %f1
; CHECK: call cosf
; CHECK: st %f0, [%fp+[[Offset1:[0-9]+]]]
; CHECK: ld [%fp+[[Offset0]]], %f1
; CHECK: call sinf
; CHECK: ld [%fp+[[Offset1]]], %f1
; CHECK: fmuls %f1, %f0, %f0
define inreg float @test_call_libfunc(float %arg0, float %arg1) {
entry:
%0 = tail call inreg float @cosf(float %arg1)
%1 = tail call inreg float @sinf(float %arg0)
%2 = fmul float %0, %1
ret float %2
}
declare inreg float @cosf(float %arg) readnone nounwind
declare inreg float @sinf(float %arg) readnone nounwind