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[mips] Add FGR_32/FGR_64/GPR_64 adjectives and use then instead of FGRPredicates/GPRPredicates
Summary: No functional change (confirmed by diffing tablegen-erated files). Depends on D3642 Reviewers: vmedic, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3645 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208213 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
parent
b49c582218
commit
0c78010b88
@ -141,23 +141,21 @@ let isCodeGenOnly = 1 in
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def MOVN_I64_S : CMov_I_F_FT<"movn.s", GPR64Opnd, FGR32Opnd, II_MOVN_S>,
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CMov_I_F_FM<19, 16>, AdditionalRequires<[IsGP64bit]>;
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let FGRPredicates = [NotFP64bit] in {
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def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM<18, 17>;
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def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM<19, 17>;
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}
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def MOVZ_I_D32 : MMRel, CMov_I_F_FT<"movz.d", GPR32Opnd, AFGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM<18, 17>, FGR_32;
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def MOVN_I_D32 : MMRel, CMov_I_F_FT<"movn.d", GPR32Opnd, AFGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM<19, 17>, FGR_32;
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let DecoderNamespace = "Mips64" in {
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def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", GPR32Opnd, FGR64Opnd, II_MOVZ_D>,
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CMov_I_F_FM<18, 17>;
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CMov_I_F_FM<18, 17>, FGR_64;
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def MOVN_I_D64 : CMov_I_F_FT<"movn.d", GPR32Opnd, FGR64Opnd, II_MOVN_D>,
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CMov_I_F_FM<19, 17>;
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CMov_I_F_FM<19, 17>, FGR_64;
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let isCodeGenOnly = 1 in {
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def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", GPR64Opnd, FGR64Opnd,
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II_MOVZ_D>, CMov_I_F_FM<18, 17>;
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II_MOVZ_D>, CMov_I_F_FM<18, 17>, FGR_64;
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def MOVN_I64_D64 : CMov_I_F_FT<"movn.d", GPR64Opnd, FGR64Opnd,
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II_MOVN_D>, CMov_I_F_FM<19, 17>;
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II_MOVN_D>, CMov_I_F_FM<19, 17>, FGR_64;
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}
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}
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@ -180,65 +178,58 @@ def MOVT_S : MMRel, CMov_F_F_FT<"movt.s", FGR32Opnd, II_MOVT_S, MipsCMovFP_T>,
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def MOVF_S : MMRel, CMov_F_F_FT<"movf.s", FGR32Opnd, II_MOVF_S, MipsCMovFP_F>,
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CMov_F_F_FM<16, 0>;
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let FGRPredicates = [NotFP64bit] in {
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def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
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MipsCMovFP_T>, CMov_F_F_FM<17, 1>;
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def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
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MipsCMovFP_F>, CMov_F_F_FM<17, 0>;
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}
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def MOVT_D32 : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D,
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MipsCMovFP_T>, CMov_F_F_FM<17, 1>, FGR_32;
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def MOVF_D32 : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D,
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MipsCMovFP_F>, CMov_F_F_FM<17, 0>, FGR_32;
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let DecoderNamespace = "Mips64" in {
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def MOVT_D64 : CMov_F_F_FT<"movt.d", FGR64Opnd, II_MOVT_D, MipsCMovFP_T>,
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CMov_F_F_FM<17, 1>;
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CMov_F_F_FM<17, 1>, FGR_64;
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def MOVF_D64 : CMov_F_F_FT<"movf.d", FGR64Opnd, II_MOVF_D, MipsCMovFP_F>,
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CMov_F_F_FM<17, 0>;
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CMov_F_F_FM<17, 0>, FGR_64;
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}
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// Instantiation of conditional move patterns.
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defm : MovzPats0<GPR32, GPR32, MOVZ_I_I, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, GPR32, MOVZ_I_I, XOR>;
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defm : MovzPats2<GPR32, GPR32, MOVZ_I_I, XORi>;
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let GPRPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>;
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defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>;
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defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>;
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defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>;
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defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>;
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defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>;
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}
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defm : MovzPats0<GPR32, GPR64, MOVZ_I_I64, SLT, SLTu, SLTi, SLTiu>, GPR_64;
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defm : MovzPats0<GPR64, GPR32, MOVZ_I_I, SLT64, SLTu64, SLTi64, SLTiu64>,
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GPR_64;
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defm : MovzPats0<GPR64, GPR64, MOVZ_I_I64, SLT64, SLTu64, SLTi64, SLTiu64>,
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GPR_64;
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defm : MovzPats1<GPR32, GPR64, MOVZ_I_I64, XOR>, GPR_64;
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defm : MovzPats1<GPR64, GPR32, MOVZ_I64_I, XOR64>, GPR_64;
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defm : MovzPats1<GPR64, GPR64, MOVZ_I64_I64, XOR64>, GPR_64;
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defm : MovzPats2<GPR32, GPR64, MOVZ_I_I64, XORi>, GPR_64;
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defm : MovzPats2<GPR64, GPR32, MOVZ_I64_I, XORi64>, GPR_64;
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defm : MovzPats2<GPR64, GPR64, MOVZ_I64_I64, XORi64>, GPR_64;
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defm : MovnPats<GPR32, GPR32, MOVN_I_I, XOR>;
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let GPRPredicates = [IsGP64bit] in {
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defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>;
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defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>;
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defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>;
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}
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defm : MovnPats<GPR32, GPR64, MOVN_I_I64, XOR>, GPR_64;
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defm : MovnPats<GPR64, GPR32, MOVN_I64_I, XOR64>, GPR_64;
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defm : MovnPats<GPR64, GPR64, MOVN_I64_I64, XOR64>, GPR_64;
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defm : MovzPats0<GPR32, FGR32, MOVZ_I_S, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, FGR32, MOVZ_I_S, XOR>;
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defm : MovnPats<GPR32, FGR32, MOVN_I_S, XOR>;
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let GPRPredicates = [IsGP64bit] in {
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>;
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defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>;
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defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>;
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}
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let FGRPredicates = [NotFP64bit] in {
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defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>;
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defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>;
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}
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let FGRPredicates = [IsFP64bit] in {
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defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>;
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defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64,
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SLTiu64>;
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defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>;
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defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>;
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defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>;
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defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>;
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}
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defm : MovzPats0<GPR64, FGR32, MOVZ_I_S, SLT64, SLTu64, SLTi64, SLTiu64>,
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GPR_64;
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defm : MovzPats1<GPR64, FGR32, MOVZ_I64_S, XOR64>, GPR_64;
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defm : MovnPats<GPR64, FGR32, MOVN_I64_S, XOR64>, GPR_64;
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defm : MovzPats0<GPR32, AFGR64, MOVZ_I_D32, SLT, SLTu, SLTi, SLTiu>, FGR_32;
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defm : MovzPats1<GPR32, AFGR64, MOVZ_I_D32, XOR>, FGR_32;
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defm : MovnPats<GPR32, AFGR64, MOVN_I_D32, XOR>, FGR_32;
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defm : MovzPats0<GPR32, FGR64, MOVZ_I_D64, SLT, SLTu, SLTi, SLTiu>, FGR_64;
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defm : MovzPats0<GPR64, FGR64, MOVZ_I_D64, SLT64, SLTu64, SLTi64, SLTiu64>,
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FGR_64;
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defm : MovzPats1<GPR32, FGR64, MOVZ_I_D64, XOR>, FGR_64;
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defm : MovzPats1<GPR64, FGR64, MOVZ_I64_D64, XOR64>, FGR_64;
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defm : MovnPats<GPR32, FGR64, MOVN_I_D64, XOR>, FGR_64;
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defm : MovnPats<GPR64, FGR64, MOVN_I64_D64, XOR64>, FGR_64;
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@ -66,6 +66,16 @@ def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">,
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def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">,
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AssemblerPredicate<"!FeatureSingleFloat">;
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//===----------------------------------------------------------------------===//
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// Mips FGR size adjectives.
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// They are mutually exclusive.
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//===----------------------------------------------------------------------===//
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class FGR_32 { list<Predicate> FGRPredicates = [NotFP64bit]; }
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class FGR_64 { list<Predicate> FGRPredicates = [IsFP64bit]; }
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//===----------------------------------------------------------------------===//
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// FP immediate patterns.
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def fpimm0 : PatLeaf<(fpimm), [{
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return N->isExactlyValue(+0.0);
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@ -266,23 +276,23 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>;
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defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>;
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defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let DecoderNamespace = "Mips64" in {
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def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
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ABSS_FM<0x8, 16>;
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ABSS_FM<0x8, 16>, FGR_64;
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def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>,
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ABSS_FM<0x8, 17>;
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ABSS_FM<0x8, 17>, FGR_64;
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def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>,
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ABSS_FM<0x9, 16>;
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ABSS_FM<0x9, 16>, FGR_64;
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def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>,
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ABSS_FM<0x9, 17>;
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ABSS_FM<0x9, 17>, FGR_64;
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def CEIL_L_S : ABSS_FT<"ceil.l.s", FGR64Opnd, FGR32Opnd, II_CEIL>,
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ABSS_FM<0xa, 16>;
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ABSS_FM<0xa, 16>, FGR_64;
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def CEIL_L_D64 : ABSS_FT<"ceil.l.d", FGR64Opnd, FGR64Opnd, II_CEIL>,
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ABSS_FM<0xa, 17>;
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ABSS_FM<0xa, 17>, FGR_64;
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def FLOOR_L_S : ABSS_FT<"floor.l.s", FGR64Opnd, FGR32Opnd, II_FLOOR>,
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ABSS_FM<0xb, 16>;
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ABSS_FM<0xb, 16>, FGR_64;
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def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>,
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ABSS_FM<0xb, 17>;
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ABSS_FM<0xb, 17>, FGR_64;
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}
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def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>,
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@ -292,26 +302,24 @@ def CVT_L_S : MMRel, ABSS_FT<"cvt.l.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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def CVT_L_D64: MMRel, ABSS_FT<"cvt.l.d", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x25, 17>;
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let FGRPredicates = [NotFP64bit] in {
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 20>;
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def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 16>;
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}
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def CVT_S_D32 : MMRel, ABSS_FT<"cvt.s.d", FGR32Opnd, AFGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>, FGR_32;
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def CVT_D32_W : MMRel, ABSS_FT<"cvt.d.w", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 20>, FGR_32;
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def CVT_D32_S : MMRel, ABSS_FT<"cvt.d.s", AFGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 16>, FGR_32;
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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let DecoderNamespace = "Mips64" in {
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def CVT_S_D64 : ABSS_FT<"cvt.s.d", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 17>;
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ABSS_FM<0x20, 17>, FGR_64;
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def CVT_S_L : ABSS_FT<"cvt.s.l", FGR32Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x20, 21>;
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ABSS_FM<0x20, 21>, FGR_64;
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def CVT_D64_W : ABSS_FT<"cvt.d.w", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 20>;
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ABSS_FM<0x21, 20>, FGR_64;
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def CVT_D64_S : ABSS_FT<"cvt.d.s", FGR64Opnd, FGR32Opnd, II_CVT>,
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ABSS_FM<0x21, 16>;
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ABSS_FM<0x21, 16>, FGR_64;
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def CVT_D64_L : ABSS_FT<"cvt.d.l", FGR64Opnd, FGR64Opnd, II_CVT>,
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ABSS_FM<0x21, 21>;
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ABSS_FM<0x21, 21>, FGR_64;
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}
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let isPseudo = 1, isCodeGenOnly = 1 in {
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@ -367,15 +375,14 @@ def FMOV_D64 : ABSS_FT<"mov.d", FGR64Opnd, FGR64Opnd, II_MOV_D>,
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def LWC1 : MMRel, LW_FT<"lwc1", FGR32Opnd, II_LWC1, load>, LW_FM<0x31>;
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def SWC1 : MMRel, SW_FT<"swc1", FGR32Opnd, II_SWC1, store>, LW_FM<0x39>;
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let FGRPredicates = [IsFP64bit], DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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let DecoderNamespace = "Mips64" in {
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def LDC164 : LW_FT<"ldc1", FGR64Opnd, II_LDC1, load>, LW_FM<0x35>, FGR_64;
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def SDC164 : SW_FT<"sdc1", FGR64Opnd, II_SDC1, store>, LW_FM<0x3d>, FGR_64;
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}
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let FGRPredicates = [NotFP64bit] in {
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def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>;
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def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>;
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}
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def LDC1 : MMRel, LW_FT<"ldc1", AFGR64Opnd, II_LDC1, load>, LW_FM<0x35>, FGR_32;
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def SDC1 : MMRel, SW_FT<"sdc1", AFGR64Opnd, II_SDC1, store>, LW_FM<0x3d>,
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FGR_32;
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/// Cop2 Memory Instructions
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def LWC2 : LW_FT<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>;
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@ -391,28 +398,31 @@ let AdditionalPredicates = [IsNotNaCl, HasFPIdx] in {
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def SWXC1 : MMRel, SWXC1_FT<"swxc1", FGR32Opnd, II_SWXC1, store>, SWXC1_FM<8>;
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}
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let FGRPredicates = [NotFP64bit],
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AdditionalPredicates = [HasFPIdx, NotInMicroMips, IsNotNaCl] in {
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def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
|
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def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
|
||||
let AdditionalPredicates = [HasFPIdx, NotInMicroMips, IsNotNaCl] in {
|
||||
def LDXC1 : LWXC1_FT<"ldxc1", AFGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
||||
FGR_32;
|
||||
def SDXC1 : SWXC1_FT<"sdxc1", AFGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
||||
FGR_32;
|
||||
}
|
||||
|
||||
let FGRPredicates = [IsFP64bit], AdditionalPredicates = [HasFPIdx],
|
||||
DecoderNamespace="Mips64" in {
|
||||
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>;
|
||||
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>;
|
||||
let AdditionalPredicates = [HasFPIdx], DecoderNamespace="Mips64" in {
|
||||
def LDXC164 : LWXC1_FT<"ldxc1", FGR64Opnd, II_LDXC1, load>, LWXC1_FM<1>,
|
||||
FGR_64;
|
||||
def SDXC164 : SWXC1_FT<"sdxc1", FGR64Opnd, II_SDXC1, store>, SWXC1_FM<9>,
|
||||
FGR_64;
|
||||
}
|
||||
|
||||
// Load/store doubleword indexed unaligned.
|
||||
let FGRPredicates = [NotFP64bit],
|
||||
AdditionalPredicates = [IsNotNaCl] in {
|
||||
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
|
||||
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
|
||||
let AdditionalPredicates = [IsNotNaCl] in {
|
||||
def LUXC1 : MMRel, LWXC1_FT<"luxc1", AFGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>,
|
||||
FGR_32;
|
||||
def SUXC1 : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>,
|
||||
FGR_32;
|
||||
}
|
||||
|
||||
let FGRPredicates = [IsFP64bit], DecoderNamespace="Mips64" in {
|
||||
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>;
|
||||
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>;
|
||||
let DecoderNamespace="Mips64" in {
|
||||
def LUXC164 : LWXC1_FT<"luxc1", FGR64Opnd, II_LUXC1>, LWXC1_FM<0x5>, FGR_64;
|
||||
def SUXC164 : SWXC1_FT<"suxc1", FGR64Opnd, II_SUXC1>, SWXC1_FM<0xd>, FGR_64;
|
||||
}
|
||||
|
||||
/// Floating-point Aritmetic
|
||||
@ -441,36 +451,31 @@ let AdditionalPredicates = [NoNaNsFPMath] in {
|
||||
MADDS_FM<7, 0>, ISA_MIPS32R2;
|
||||
}
|
||||
|
||||
let FGRPredicates = [NotFP64bit] in {
|
||||
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
|
||||
MADDS_FM<4, 1>, ISA_MIPS32R2;
|
||||
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
|
||||
MADDS_FM<5, 1>, ISA_MIPS32R2;
|
||||
}
|
||||
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
|
||||
MADDS_FM<4, 1>, ISA_MIPS32R2, FGR_32;
|
||||
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
|
||||
MADDS_FM<5, 1>, ISA_MIPS32R2, FGR_32;
|
||||
|
||||
let FGRPredicates = [NotFP64bit],
|
||||
AdditionalPredicates = [NoNaNsFPMath] in {
|
||||
let AdditionalPredicates = [NoNaNsFPMath] in {
|
||||
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
|
||||
MADDS_FM<6, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<6, 1>, ISA_MIPS32R2, FGR_32;
|
||||
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
|
||||
MADDS_FM<7, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<7, 1>, ISA_MIPS32R2, FGR_32;
|
||||
}
|
||||
|
||||
let FGRPredicates = [IsFP64bit],
|
||||
isCodeGenOnly=1 in {
|
||||
let isCodeGenOnly=1 in {
|
||||
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
|
||||
MADDS_FM<4, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<4, 1>, ISA_MIPS32R2, FGR_64;
|
||||
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
|
||||
MADDS_FM<5, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<5, 1>, ISA_MIPS32R2, FGR_64;
|
||||
}
|
||||
|
||||
let FGRPredicates = [IsFP64bit],
|
||||
AdditionalPredicates = [NoNaNsFPMath],
|
||||
let AdditionalPredicates = [NoNaNsFPMath],
|
||||
isCodeGenOnly=1 in {
|
||||
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
|
||||
MADDS_FM<6, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<6, 1>, ISA_MIPS32R2, FGR_64;
|
||||
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
|
||||
MADDS_FM<7, 1>, ISA_MIPS32R2;
|
||||
MADDS_FM<7, 1>, ISA_MIPS32R2, FGR_64;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -561,53 +566,45 @@ def : MipsPat<(f32 (sint_to_fp GPR32Opnd:$src)),
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_W_S FGR32Opnd:$src)>;
|
||||
|
||||
let FGRPredicates = [NotFP64bit] in {
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D32_W GPR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
||||
(TRUNC_W_D32 AFGR64Opnd:$src)>;
|
||||
def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
|
||||
(CVT_S_D32 AFGR64Opnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D32_S FGR32Opnd:$src)>;
|
||||
}
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32;
|
||||
def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src),
|
||||
(TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32;
|
||||
def : MipsPat<(f32 (fround AFGR64Opnd:$src)),
|
||||
(CVT_S_D32 AFGR64Opnd:$src)>, FGR_32;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D32_S FGR32Opnd:$src)>, FGR_32;
|
||||
|
||||
let FGRPredicates = [IsFP64bit] in {
|
||||
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>;
|
||||
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>;
|
||||
def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64;
|
||||
def : MipsPat<(f64 fpimm0neg), (FNEG_D64 (DMTC1 ZERO_64))>, FGR_64;
|
||||
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D64_W GPR32Opnd:$src)>;
|
||||
def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
|
||||
(EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>;
|
||||
def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
|
||||
(PseudoCVT_D64_L GPR64Opnd:$src)>;
|
||||
def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)),
|
||||
(PseudoCVT_D64_W GPR32Opnd:$src)>, FGR_64;
|
||||
def : MipsPat<(f32 (sint_to_fp GPR64Opnd:$src)),
|
||||
(EXTRACT_SUBREG (PseudoCVT_S_L GPR64Opnd:$src), sub_lo)>, FGR_64;
|
||||
def : MipsPat<(f64 (sint_to_fp GPR64Opnd:$src)),
|
||||
(PseudoCVT_D64_L GPR64Opnd:$src)>, FGR_64;
|
||||
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_W_D64 FGR64Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_L_S FGR32Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_L_D64 FGR64Opnd:$src)>;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_W_D64 FGR64Opnd:$src)>, FGR_64;
|
||||
def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src),
|
||||
(TRUNC_L_S FGR32Opnd:$src)>, FGR_64;
|
||||
def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src),
|
||||
(TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64;
|
||||
|
||||
def : MipsPat<(f32 (fround FGR64Opnd:$src)),
|
||||
(CVT_S_D64 FGR64Opnd:$src)>;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D64_S FGR32Opnd:$src)>;
|
||||
}
|
||||
def : MipsPat<(f32 (fround FGR64Opnd:$src)),
|
||||
(CVT_S_D64 FGR64Opnd:$src)>, FGR_64;
|
||||
def : MipsPat<(f64 (fextend FGR32Opnd:$src)),
|
||||
(CVT_D64_S FGR32Opnd:$src)>, FGR_64;
|
||||
|
||||
// Patterns for loads/stores with a reg+imm operand.
|
||||
let AddedComplexity = 40 in {
|
||||
def : LoadRegImmPat<LWC1, f32, load>;
|
||||
def : StoreRegImmPat<SWC1, f32>;
|
||||
|
||||
let FGRPredicates = [IsFP64bit] in {
|
||||
def : LoadRegImmPat<LDC164, f64, load>;
|
||||
def : StoreRegImmPat<SDC164, f64>;
|
||||
}
|
||||
def : LoadRegImmPat<LDC164, f64, load>, FGR_64;
|
||||
def : StoreRegImmPat<SDC164, f64>, FGR_64;
|
||||
|
||||
let FGRPredicates = [NotFP64bit] in {
|
||||
def : LoadRegImmPat<LDC1, f64, load>;
|
||||
def : StoreRegImmPat<SDC1, f64>;
|
||||
}
|
||||
def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
|
||||
def : StoreRegImmPat<SDC1, f64>, FGR_32;
|
||||
}
|
||||
|
||||
@ -194,6 +194,13 @@ def IsLE : Predicate<"Subtarget.isLittle()">;
|
||||
def IsBE : Predicate<"!Subtarget.isLittle()">;
|
||||
def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips GPR size adjectives.
|
||||
// They are mutually exclusive.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Mips ISA/ASE membership and instruction group membership adjectives.
|
||||
// They are mutually exclusive.
|
||||
|
||||
Loading…
Reference in New Issue
Block a user