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Doxygenify some comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15360 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -147,27 +147,23 @@ public:
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return get(Opcode).Flags & M_TERMINATOR_FLAG;
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}
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//
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// Return true if the instruction is a register to register move and
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// leave the source and dest operands in the passed parameters.
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//
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/// Return true if the instruction is a register to register move
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/// and leave the source and dest operands in the passed parameters.
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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return false;
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}
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//
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// Insert a goto (unconditional branch) sequence to MBB, right
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// before MBBI
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/// Insert a goto (unconditional branch) sequence to MBB, right
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/// before MBBI
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virtual void insertGoto(const MachineBasicBlock& MBB,
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MachineBasicBlock::iterator MBBI) const {
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assert(0 && "Target didn't implement insertGoto!");
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}
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//
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// Reverses the branch condition of the MachineInstr pointed by
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// MI. The instruction is replaced and the new MI is returned.
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/// Reverses the branch condition of the MachineInstr pointed by
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/// MI. The instruction is replaced and the new MI is returned.
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virtual MachineBasicBlock::iterator
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reverseBranchCondition(MachineBasicBlock::iterator MI) const {
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assert(0 && "Target didn't implement reverseBranchCondition!");
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