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Don't re-use existing addrec expansions if they contain casts.
This fixes PR9259. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -858,7 +858,8 @@ SCEVExpander::getAddRecExprPHILiterally(const SCEVAddRecExpr *Normalized,
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// loop already visited by LSR for example, but it wouldn't have
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// to be.
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do {
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if (IncV->getNumOperands() == 0 || isa<PHINode>(IncV)) {
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if (IncV->getNumOperands() == 0 || isa<PHINode>(IncV) ||
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isa<CastInst>(IncV)) {
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IncV = 0;
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break;
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}
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22
test/CodeGen/X86/lsr-quadratic-expand.ll
Normal file
22
test/CodeGen/X86/lsr-quadratic-expand.ll
Normal file
@ -0,0 +1,22 @@
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; RUN: llc -march=x86-64 < %s
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define void @dw2102_i2c_transfer() nounwind {
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entry:
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br label %bb
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bb: ; preds = %bb, %entry
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%z = phi i64 [ 0, %entry ], [ %z3, %bb ]
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%z1 = phi i16 [ undef, %entry ], [ %z6, %bb ]
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%z2 = phi i32 [ 0, %entry ], [ %z8, %bb ]
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%z3 = add i64 %z, 1
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%z4 = zext i16 %z1 to i32
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%z5 = add nsw i32 %z4, %z2
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%z6 = trunc i32 %z5 to i16
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call fastcc void @dw210x_op_rw(i16 zeroext %z6)
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%z7 = getelementptr i8* null, i64 %z
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store i8 undef, i8* %z7, align 1
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%z8 = add nsw i32 %z2, 1
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br label %bb
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}
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declare fastcc void @dw210x_op_rw(i16 zeroext) nounwind
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