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https://github.com/c64scene-ar/llvm-6502.git
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Revert this patch for the time being. Needs more testing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97099 91177308-0d34-0410-b5e6-96231b3b80d8
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Scott Michel
parent
4c61cdd307
commit
0d0840108f
@ -66,6 +66,9 @@ namespace llvm {
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//! Predicate test for an unsigned 10-bit value
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/*!
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\param Value The input value to be tested
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This predicate tests for an unsigned 10-bit value, returning the 10-bit value
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as a short if true.
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*/
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inline bool isU10Constant(short Value) {
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return (Value == (Value & 0x3ff));
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@ -87,70 +90,6 @@ namespace llvm {
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return (Value == (Value & 0x3ff));
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}
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//! Predicate test for a signed 14-bit value
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/*!
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\param Value The input value to be tested
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*/
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template<typename T>
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inline bool isS14Constant(T Value);
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template<>
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inline bool isS14Constant<short>(short Value) {
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return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
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}
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template<>
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inline bool isS14Constant<int>(int Value) {
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return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
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}
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template<>
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inline bool isS14Constant<uint32_t>(uint32_t Value) {
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return (Value <= ((1 << 13) - 1));
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}
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template<>
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inline bool isS14Constant<int64_t>(int64_t Value) {
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return (Value >= -(1 << 13) && Value <= (1 << 13) - 1);
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}
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template<>
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inline bool isS14Constant<uint64_t>(uint64_t Value) {
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return (Value <= ((1 << 13) - 1));
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}
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//! Predicate test for a signed 16-bit value
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/*!
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\param Value The input value to be tested
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*/
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template<typename T>
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inline bool isS16Constant(T Value);
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template<>
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inline bool isS16Constant<short>(short Value) {
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return true;
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}
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template<>
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inline bool isS16Constant<int>(int Value) {
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return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
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}
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template<>
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inline bool isS16Constant<uint32_t>(uint32_t Value) {
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return (Value <= ((1 << 15) - 1));
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}
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template<>
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inline bool isS16Constant<int64_t>(int64_t Value) {
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return (Value >= -(1 << 15) && Value <= (1 << 15) - 1);
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}
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template<>
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inline bool isS16Constant<uint64_t>(uint64_t Value) {
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return (Value <= ((1 << 15) - 1));
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}
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extern Target TheCellSPUTarget;
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}
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@ -28,7 +28,6 @@
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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@ -336,7 +335,6 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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DebugLoc dl = II->getDebugLoc();
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while (!MI.getOperand(i).isFI()) {
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++i;
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@ -365,22 +363,11 @@ SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
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// Replace the FrameIndex with base register with $sp (aka $r1)
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SPOp.ChangeToRegister(SPU::R1, false);
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// if 'Offset' doesn't fit to the D-form instruction's
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// immediate, convert the instruction to X-form
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// if the instruction is not an AI (which takes a s10 immediate), assume
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// it is a load/store that can take a s14 immediate
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if ( (MI.getOpcode() == SPU::AIr32 && !isS10Constant(Offset))
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|| !isS14Constant(Offset) ) {
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int newOpcode = convertDFormToXForm(MI.getOpcode());
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unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
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BuildMI(MBB, II, dl, TII.get(SPU::ILr32), tmpReg )
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.addImm(Offset);
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BuildMI(MBB, II, dl, TII.get(newOpcode), MI.getOperand(0).getReg())
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.addReg(tmpReg, RegState::Kill)
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.addReg(SPU::R1);
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// remove the replaced D-form instruction
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MBB.erase(II);
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if (Offset > SPUFrameInfo::maxFrameOffset()
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|| Offset < SPUFrameInfo::minFrameOffset()) {
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errs() << "Large stack adjustment ("
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<< Offset
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<< ") in SPURegisterInfo::eliminateFrameIndex.";
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} else {
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MO.ChangeToImmediate(Offset);
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}
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@ -435,14 +422,6 @@ void SPURegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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MF.getRegInfo().setPhysRegUnused(SPU::R0);
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MF.getRegInfo().setPhysRegUnused(SPU::R1);
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MF.getRegInfo().setPhysRegUnused(SPU::R2);
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MachineFrameInfo *MFI = MF.getFrameInfo();
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const TargetRegisterClass *RC = &SPU::R32CRegClass;
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RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
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RC->getAlignment(),
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false));
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}
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void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
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@ -487,7 +466,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
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// Adjust $sp by required amout
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BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1)
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.addImm(FrameSize);
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} else if (isS16Constant(FrameSize)) {
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} else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) {
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// Frame size can be loaded into ILr32n, so temporarily spill $r2 and use
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// $r2 to adjust $sp:
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BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2)
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@ -495,7 +474,7 @@ void SPURegisterInfo::emitPrologue(MachineFunction &MF) const
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.addReg(SPU::R1);
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BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2)
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.addImm(FrameSize);
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BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1)
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BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1)
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.addReg(SPU::R2)
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.addReg(SPU::R1);
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BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1)
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@ -594,7 +573,7 @@ SPURegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const
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.addReg(SPU::R2);
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BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0)
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.addImm(16)
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.addReg(SPU::R1);
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.addReg(SPU::R2);
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BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2).
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addReg(SPU::R2)
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.addImm(16);
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@ -638,42 +617,4 @@ SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
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return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
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}
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int
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SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
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{
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switch(dFormOpcode)
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{
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case SPU::AIr32: return SPU::Ar32;
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case SPU::LQDr32: return SPU::LQXr32;
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case SPU::LQDr128: return SPU::LQXr128;
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case SPU::LQDv16i8: return SPU::LQXv16i8;
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case SPU::LQDv4f32: return SPU::LQXv4f32;
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case SPU::STQDr32: return SPU::STQXr32;
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case SPU::STQDr128: return SPU::STQXr128;
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case SPU::STQDv4i32: return SPU::STQXv4i32;
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case SPU::STQDv4f32: return SPU::STQXv4f32;
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default: assert( false && "Unhandled D to X-form conversion");
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}
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// default will assert, but need to return something to keep the
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// compiler happy.
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return dFormOpcode;
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}
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// TODO this is already copied from PPC. Could this convenience function
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// be moved to the RegScavenger class?
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unsigned
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SPURegisterInfo::findScratchRegister(MachineBasicBlock::iterator II,
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RegScavenger *RS,
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const TargetRegisterClass *RC,
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int SPAdj) const
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{
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assert(RS && "Register scavenging must be on");
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unsigned Reg = RS->FindUnusedReg(RC);
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if (Reg == 0)
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Reg = RS->scavengeRegister(RC, II, SPAdj);
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assert( Reg && "Register scavenger failed");
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return Reg;
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}
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#include "SPUGenRegisterInfo.inc"
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@ -53,10 +53,6 @@ namespace llvm {
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virtual const TargetRegisterClass* const *
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getCalleeSavedRegClasses(const MachineFunction *MF) const;
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//! Allow for scavenging, so we can get scratch registers when needed.
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virtual bool requiresRegisterScavenging(const MachineFunction &MF) const
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{ return true; }
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//! Return the reserved registers
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BitVector getReservedRegs(const MachineFunction &MF) const;
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@ -101,21 +97,6 @@ namespace llvm {
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//! Get DWARF debugging register number
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int getDwarfRegNum(unsigned RegNum, bool isEH) const;
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//! Convert D-form load/store to X-form load/store
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/*!
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Converts a regiser displacement load/store into a register-indexed
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load/store for large stack frames, when the stack frame exceeds the
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range of a s10 displacement.
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*/
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int convertDFormToXForm(int dFormOpcode) const;
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//! Acquire an unused register in an emergency.
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unsigned findScratchRegister(MachineBasicBlock::iterator II,
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RegScavenger *RS,
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const TargetRegisterClass *RC,
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int SPAdj) const;
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};
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} // end namespace llvm
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