6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-09-24 23:28:41 +00:00
Code Issues Projects Releases Wiki Activity

Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137502 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2011-08-12 20:36:11 +00:00
parent e6e8826870
commit 0d09499cf3
3 changed files with 483 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

29
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@@ -129,8 +129,6 @@ static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
@@ -970,6 +968,7 @@ static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::LDRB_POST_IMM:
case ARM::LDRB_POST_REG:
case ARM::LDR_PRE:
case ARM::LDRB_PRE:
case ARM::LDRBT_POST_REG:
case ARM::LDRBT_POST_IMM:
case ARM::LDRT_POST_REG:
@@ -1123,6 +1122,15 @@ static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
case ARM::LDRD:
case ARM::LDRD_PRE:
case ARM::LDRD_POST:
case ARM::LDRH:
case ARM::LDRH_PRE:
case ARM::LDRH_POST:
case ARM::LDRSH:
case ARM::LDRSH_PRE:
case ARM::LDRSH_POST:
case ARM::LDRSB:
case ARM::LDRSB_PRE:
case ARM::LDRSB_POST:
case ARM::LDRHTr:
case ARM::LDRSBTr:
if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
@@ -2451,23 +2459,6 @@ static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
return true;
}
static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
bool isImm = fieldFromInstruction32(Val, 9, 1);
bool isAdd = fieldFromInstruction32(Val, 8, 1);
unsigned imm = fieldFromInstruction32(Val, 0, 8);
if (!isImm) {
if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false;
Inst.addOperand(MCOperand::CreateImm(!isAdd << 8));
} else {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8)));
}
return true;
}
static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
switch (Val) {