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Moved InsertCallerSaveInstr to the SparcRegInfo.cpp and made machine independent

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
2001-11-03 17:14:13 +00:00
parent ef1b0cb9a5
commit 0d3ea0268f
3 changed files with 10 additions and 7 deletions
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4
include/llvm/Target/MachineInstrInfo.h
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@@ -166,13 +166,13 @@ public:
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG;
}
bool isDummyPhiInstr(MachineOpCode opCode) const {
bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
}
// delete this later *******
bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
// Check if an instruction can be issued before its operands are ready,

4
include/llvm/Target/TargetInstrInfo.h
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@@ -166,13 +166,13 @@ public:
|| getDescriptor(opCode).iclass & M_PREFETCH_FLAG
|| getDescriptor(opCode).iclass & M_STORE_FLAG;
}
bool isDummyPhiInstr(MachineOpCode opCode) const {
bool isDummyPhiInstr(const MachineOpCode opCode) const {
return getDescriptor(opCode).iclass & M_DUMMY_PHI_FLAG;
}
// delete this later *******
bool isPhi(MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
bool isPhi(const MachineOpCode opCode) { return isDummyPhiInstr(opCode); }
// Check if an instruction can be issued before its operands are ready,

3
include/llvm/Target/TargetRegInfo.h
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@@ -150,6 +150,9 @@ public:
cpMem2RegMI(const unsigned SrcPtrReg, const int Offset,
const unsigned DestReg, const int RegType) const=0;
virtual MachineInstr *cpValue2Value( Value *Src, Value *Dest) const=0;
virtual bool isRegVolatile(const int RegClassID, const int Reg) const=0;