From 0d48d6106e7ab165bcf80b5ba6b43ff3216f2644 Mon Sep 17 00:00:00 2001
From: Bob Wilson <bob.wilson@apple.com>
Date: Wed, 4 Nov 2009 19:25:34 +0000
Subject: [PATCH] Add test for ARM indirectbr codegen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86042 91177308-0d34-0410-b5e6-96231b3b80d8
---
 test/CodeGen/ARM/indirectbr.ll | 63 ++++++++++++++++++++++++++++++++++
 1 file changed, 63 insertions(+)
 create mode 100644 test/CodeGen/ARM/indirectbr.ll

diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll
new file mode 100644
index 00000000000..224f34574dc
--- /dev/null
+++ b/test/CodeGen/ARM/indirectbr.ll
@@ -0,0 +1,63 @@
+; RUN: llc < %s -relocation-model=pic -march=arm | FileCheck %s -check-prefix=ARM
+; RUN: llc < %s -relocation-model=pic -march=thumb | FileCheck %s -check-prefix=THUMB
+; RUN: llc < %s -relocation-model=static -march=thumb -mattr=+thumb2 | FileCheck %s -check-prefix=THUMB2
+
+@nextaddr = global i8* null                       ; <i8**> [#uses=2]
+@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
+
+define internal arm_apcscc i32 @foo(i32 %i) nounwind {
+; ARM: foo:
+; THUMB: foo:
+; THUMB2: foo:
+entry:
+  %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
+  %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
+  br i1 %1, label %bb3, label %bb2
+
+bb2:                                              ; preds = %entry, %bb3
+  %gotovar.4.0 = phi i8* [ %gotovar.4.0.pre, %bb3 ], [ %0, %entry ] ; <i8*> [#uses=1]
+; ARM: bx
+; THUMB: mov pc, r1
+; THUMB2: mov pc, r1
+  indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1]
+
+bb3:                                              ; preds = %entry
+  %2 = getelementptr inbounds [5 x i8*]* @C.0.2070, i32 0, i32 %i ; <i8**> [#uses=1]
+  %gotovar.4.0.pre = load i8** %2, align 4        ; <i8*> [#uses=1]
+  br label %bb2
+
+L5:                                               ; preds = %bb2
+  br label %L4
+
+L4:                                               ; preds = %L5, %bb2
+  %res.0 = phi i32 [ 385, %L5 ], [ 35, %bb2 ]     ; <i32> [#uses=1]
+  br label %L3
+
+L3:                                               ; preds = %L4, %bb2
+  %res.1 = phi i32 [ %res.0, %L4 ], [ 5, %bb2 ]   ; <i32> [#uses=1]
+  br label %L2
+
+L2:                                               ; preds = %L3, %bb2
+  %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ]   ; <i32> [#uses=1]
+  %phitmp = mul i32 %res.2, 6                     ; <i32> [#uses=1]
+  br label %L1
+
+L1:                                               ; preds = %L2, %bb2
+  %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ]  ; <i32> [#uses=1]
+; ARM: ldr r1, LCPI1_2
+; ARM: add r1, pc, r1
+; ARM: str r1
+; THUMB: ldr r2, LCPI1_4
+; THUMB: add r2, pc
+; THUMB: str r2
+; THUMB2: ldr r2, LCPI1_2
+; THUMB2-NEXT: str r2
+  store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
+  ret i32 %res.3
+}
+; ARM: LCPI1_2:
+; ARM-NEXT: .long L_foo_L5-(LPC2+8)
+; THUMB: LCPI1_4:
+; THUMB-NEXT: .long L_foo_L5-(LPC2+4)
+; THUMB2: LCPI1_2:
+; THUMB2-NEXT: .long L_foo_L5