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https://github.com/c64scene-ar/llvm-6502.git
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1. Refactored handling of integer immediate values for add, or, xor and sub.
New routine: ISel::SelectIntImmediateExpr
2. Now checking use counts of large constants. If use count is > 2 then drop
thru so that the constant gets loaded into a register.
Source:
int %test1(int %a) {
entry:
%tmp.1 = add int %a, 123456789 ; <int> [#uses=1]
%tmp.2 = or int %tmp.1, 123456789 ; <int> [#uses=1]
%tmp.3 = xor int %tmp.2, 123456789 ; <int> [#uses=1]
%tmp.4 = sub int %tmp.3, -123456789 ; <int> [#uses=1]
ret int %tmp.4
}
Did Emit:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
addi r2, r3, -13035
addis r2, r2, 1884
ori r2, r2, 52501
oris r2, r2, 1883
xori r2, r2, 52501
xoris r2, r2, 1883
addi r2, r2, 52501
addis r3, r2, 1883
blr
Now Emits:
.machine ppc970
.text
.align 2
.globl _test1
_test1:
.LBB_test1_0: ; entry
lis r2, 1883
ori r2, r2, 52501
add r3, r3, r2
or r3, r3, r2
xor r3, r3, r2
add r3, r3, r2
blr
Patch by Jim Laskey!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22749 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d2ff5ef654
commit
0d7d99fd44
@ -569,6 +569,9 @@ public:
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unsigned FoldIfWideZeroExtend(SDOperand N);
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unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
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unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
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bool SelectIntImmediateExpr(SDOperand N, unsigned Result, unsigned C,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic);
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unsigned SelectExpr(SDOperand N, bool Recording=false);
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void Select(SDOperand N);
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@ -1275,6 +1278,45 @@ void ISel::SelectBranchCC(SDOperand N)
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return;
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}
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// SelectIntImmediateExpr - Choose code for opcodes with immediate value.
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// Note: immediate constant must be second operand so that the use count can be
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// determined.
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bool ISel::SelectIntImmediateExpr(SDOperand N, unsigned Result, unsigned C,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic) {
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// get the hi and lo portions of constant
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unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
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unsigned Lo = Lo16(C);
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// assume no intermediate result from lo instruction (same as final result)
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unsigned Tmp = Result;
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// check if two instructions are needed
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if (Hi && Lo) {
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// exit if usage indicates it would be better to load immediate into a
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// register
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if (dyn_cast<ConstantSDNode>(N.getOperand(1))->use_size() > 2)
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return false;
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// need intermediate result for two instructions
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Tmp = MakeReg(MVT::i32);
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}
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// get first operand
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unsigned Opr0 = SelectExpr(N.getOperand(0));
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// is a lo instruction needed
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if (Lo) {
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// generate instruction for hi portion
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const MachineInstrBuilder &MIBLo = BuildMI(BB, OCLo, 2, Tmp).addReg(Opr0);
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if (IsArithmetic) MIBLo.addSImm(Lo); else MIBLo.addImm(Lo);
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// need to switch out first operand for hi instruction
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Opr0 = Tmp;
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}
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// is a ho instruction needed
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if (Hi) {
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// generate instruction for hi portion
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const MachineInstrBuilder &MIBHi = BuildMI(BB, OCHi, 2, Result).addReg(Opr0);
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if (IsArithmetic) MIBHi.addSImm(Hi); else MIBHi.addImm(Hi);
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}
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return true;
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}
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unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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unsigned Result;
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unsigned Tmp1, Tmp2, Tmp3;
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@ -1636,22 +1678,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = HA16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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unsigned Reg = MakeReg(MVT::i32);
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BuildMI(BB, PPC::ADDI, 2, Reg).addReg(Tmp1).addSImm(Tmp2);
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BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Reg).addSImm(Tmp3);
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} else if (Tmp2) {
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BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
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} else {
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BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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}
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return Result;
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if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::ADDIS, PPC::ADDI, true))
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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@ -1706,26 +1738,16 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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case ISD::OR:
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if (SelectBitfieldInsert(N, Result))
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return Result;
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = Hi16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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unsigned Reg = MakeReg(MVT::i32);
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BuildMI(BB, PPC::ORI, 2, Reg).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, PPC::ORIS, 2, Result).addReg(Reg).addImm(Tmp3);
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} else if (Tmp2) {
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BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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BuildMI(BB, PPC::ORIS, 2, Result).addReg(Tmp1).addImm(Tmp3);
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}
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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Opc = Recording ? PPC::ORo : PPC::OR;
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RecordSuccess = true;
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::ORIS, PPC::ORI, false))
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return Result;
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}
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// emit regular or
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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Opc = Recording ? PPC::ORo : PPC::OR;
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RecordSuccess = true;
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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case ISD::XOR: {
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@ -1763,23 +1785,14 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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}
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp3 = Hi16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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unsigned Reg = MakeReg(MVT::i32);
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BuildMI(BB, PPC::XORI, 2, Reg).addReg(Tmp1).addImm(Tmp2);
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BuildMI(BB, PPC::XORIS, 2, Result).addReg(Reg).addImm(Tmp3);
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} else if (Tmp2) {
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BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
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} else {
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BuildMI(BB, PPC::XORIS, 2, Result).addReg(Tmp1).addImm(Tmp3);
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}
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} else {
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
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if (SelectIntImmediateExpr(N, Result, Tmp2, PPC::XORIS, PPC::XORI, false))
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return Result;
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}
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// emit regular xor
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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BuildMI(BB, PPC::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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}
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@ -1816,20 +1829,8 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
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BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
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return Result;
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} else if (isIntImmediate(N.getOperand(1), Tmp2)) {
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = -Tmp2;
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Tmp3 = HA16(Tmp2);
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Tmp2 = Lo16(Tmp2);
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if (Tmp2 && Tmp3) {
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unsigned Reg = MakeReg(MVT::i32);
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BuildMI(BB, PPC::ADDI, 2, Reg).addReg(Tmp1).addSImm(Tmp2);
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BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Reg).addSImm(Tmp3);
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} else if (Tmp2) {
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BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
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} else {
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BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp3);
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}
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return Result;
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if (SelectIntImmediateExpr(N, Result, -Tmp2, PPC::ADDIS, PPC::ADDI, true))
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return Result;
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}
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Tmp1 = SelectExpr(N.getOperand(0));
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Tmp2 = SelectExpr(N.getOperand(1));
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