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AArch64: Don't lower ISD::SELECT to ISD::SELECT_CC
Instead of lowering SELECT to SELECT_CC which is further lowered later immediately call the SELECT_CC lowering code. This is preferable because: - Avoids an unnecessary roundtrip through the legalization queues with an intermediate node. - More importantly: Lowered operations get visited last leading to SELECT_CC getting visited with legalized operands and unlegalized ones for preexisting SELECT_CC nodes. This does not hurt the current code (hence no testcase) but is required for another patch I am working on. Differential Revision: http://reviews.llvm.org/D8187 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@234334 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -3515,49 +3515,10 @@ static bool selectCCOpsAreFMaxCompatible(SDValue Cmp, SDValue Result) {
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return Result->getOpcode() == ISD::FP_EXTEND && Result->getOperand(0) == Cmp;
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}
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SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue CC = Op->getOperand(0);
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SDValue TVal = Op->getOperand(1);
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SDValue FVal = Op->getOperand(2);
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SDLoc DL(Op);
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unsigned Opc = CC.getOpcode();
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// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
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// instruction.
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if (CC.getResNo() == 1 &&
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(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
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// Only lower legal XALUO ops.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(CC->getValueType(0)))
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return SDValue();
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AArch64CC::CondCode OFCC;
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SDValue Value, Overflow;
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std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CC.getValue(0), DAG);
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SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
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return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
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CCVal, Overflow);
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}
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if (CC.getOpcode() == ISD::SETCC)
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return DAG.getSelectCC(DL, CC.getOperand(0), CC.getOperand(1), TVal, FVal,
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cast<CondCodeSDNode>(CC.getOperand(2))->get());
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else
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return DAG.getSelectCC(DL, CC, DAG.getConstant(0, CC.getValueType()), TVal,
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FVal, ISD::SETNE);
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}
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SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
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SDValue AArch64TargetLowering::LowerSELECT_CC(ISD::CondCode CC, SDValue LHS,
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SDValue RHS, SDValue TVal,
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SDValue FVal, SDLoc dl,
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SelectionDAG &DAG) const {
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue TVal = Op.getOperand(2);
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SDValue FVal = Op.getOperand(3);
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SDLoc dl(Op);
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// Handle f128 first, because it will result in a comparison of some RTLIB
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// call result against zero.
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if (LHS.getValueType() == MVT::f128) {
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@ -3665,14 +3626,14 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
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SDValue CCVal;
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SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
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EVT VT = Op.getValueType();
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EVT VT = TVal.getValueType();
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return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);
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}
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// Now we know we're dealing with FP values.
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assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
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assert(LHS.getValueType() == RHS.getValueType());
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EVT VT = Op.getValueType();
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EVT VT = TVal.getValueType();
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// Try to match this select into a max/min operation, which have dedicated
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// opcode in the instruction set.
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@ -3733,6 +3694,58 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
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return CS1;
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}
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SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
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SelectionDAG &DAG) const {
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ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
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SDValue LHS = Op.getOperand(0);
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SDValue RHS = Op.getOperand(1);
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SDValue TVal = Op.getOperand(2);
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SDValue FVal = Op.getOperand(3);
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SDLoc DL(Op);
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return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
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}
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SDValue AArch64TargetLowering::LowerSELECT(SDValue Op,
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SelectionDAG &DAG) const {
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SDValue CCVal = Op->getOperand(0);
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SDValue TVal = Op->getOperand(1);
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SDValue FVal = Op->getOperand(2);
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SDLoc DL(Op);
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unsigned Opc = CCVal.getOpcode();
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// Optimize {s|u}{add|sub|mul}.with.overflow feeding into a select
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// instruction.
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if (CCVal.getResNo() == 1 &&
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(Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
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Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) {
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// Only lower legal XALUO ops.
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if (!DAG.getTargetLoweringInfo().isTypeLegal(CCVal->getValueType(0)))
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return SDValue();
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AArch64CC::CondCode OFCC;
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SDValue Value, Overflow;
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std::tie(Value, Overflow) = getAArch64XALUOOp(OFCC, CCVal.getValue(0), DAG);
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SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);
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return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,
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CCVal, Overflow);
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}
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// Lower it the same way as we would lower a SELECT_CC node.
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ISD::CondCode CC;
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SDValue LHS, RHS;
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if (CCVal.getOpcode() == ISD::SETCC) {
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LHS = CCVal.getOperand(0);
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RHS = CCVal.getOperand(1);
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CC = cast<CondCodeSDNode>(CCVal->getOperand(2))->get();
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} else {
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LHS = CCVal;
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RHS = DAG.getConstant(0, CCVal.getValueType());
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CC = ISD::SETNE;
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}
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return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);
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}
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SDValue AArch64TargetLowering::LowerJumpTable(SDValue Op,
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SelectionDAG &DAG) const {
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// Jump table entries as PC relative offsets. No additional tweaking
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@ -420,6 +420,9 @@ private:
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(ISD::CondCode CC, SDValue LHS, SDValue RHS,
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SDValue TVal, SDValue FVal, SDLoc dl,
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SelectionDAG &DAG) const;
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SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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