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https://github.com/c64scene-ar/llvm-6502.git
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Add hasExtraSrcRegAllocReq and hasExtraDefRegAllocReq flags to ld / st multiple,
ld / st pairs, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83197 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
799d697bf8
commit
0d92f5f768
@ -628,7 +628,8 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in
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// FIXME: remove when we have a way to marking a MI with these properties.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def LDM_RET : AXI4ld<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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LdStMulFrm, IIC_Br, "ldm${p}${addr:submode} $addr, $wb",
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@ -783,7 +784,7 @@ def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoadr, "ldr", "sb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
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let mayLoad = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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def LDRD : AI3ldd<(outs GPR:$dst1, GPR:$dst2), (ins addrmode3:$addr), LdMiscFrm,
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IIC_iLoadr, "ldr", "d $dst1, $addr",
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@ -846,7 +847,7 @@ def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm, IIC_iStorer,
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[(truncstorei8 GPR:$src, addrmode2:$addr)]>;
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// Store doubleword
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let mayStore = 1 in
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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def STRD : AI3std<(outs), (ins GPR:$src1, GPR:$src2, addrmode3:$addr),
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StMiscFrm, IIC_iStorer,
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"str", "d $src1, $addr", []>, Requires<[IsARM, HasV5TE]>;
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@ -898,13 +899,13 @@ def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1 in
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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def LDM : AXI4ld<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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LdStMulFrm, IIC_iLoadm, "ldm${p}${addr:submode} $addr, $wb",
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[]>;
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let mayStore = 1 in
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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def STM : AXI4st<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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LdStMulFrm, IIC_iStorem, "stm${p}${addr:submode} $addr, $wb",
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@ -107,7 +107,7 @@ def addrmode_neonldstm : Operand<i32>,
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//===----------------------------------------------------------------------===//
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/* TODO: Take advantage of vldm.
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let mayLoad = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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def VLDMD : NI<(outs),
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(ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops),
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IIC_fpLoadm,
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@ -176,7 +176,7 @@ def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1>;
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def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1>;
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def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1>;
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let mayLoad = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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// VLD2 : Vector Load (multiple 2-element structures)
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class VLD2D<string OpcodeStr>
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@ -245,7 +245,7 @@ class VLD4LND<string OpcodeStr>
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def VLD4LNd8 : VLD4LND<"vld4.8">;
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def VLD4LNd16 : VLD4LND<"vld4.16">;
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def VLD4LNd32 : VLD4LND<"vld4.32">;
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}
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} // mayLoad = 1, hasExtraDefRegAllocReq = 1
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// VST1 : Vector Store (multiple single elements)
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class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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@ -257,6 +257,7 @@ class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp>
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!strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), "",
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[(IntOp addrmode6:$addr, (Ty QPR:$src))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1>;
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def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1>;
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def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1>;
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@ -268,8 +269,9 @@ def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1>;
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def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1>;
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def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1>;
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def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1>;
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} // hasExtraSrcRegAllocReq
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let mayStore = 1 in {
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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// VST2 : Vector Store (multiple 2-element structures)
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class VST2D<string OpcodeStr>
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@ -334,7 +336,7 @@ class VST4LND<string OpcodeStr>
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def VST4LNd8 : VST4LND<"vst4.8">;
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def VST4LNd16 : VST4LND<"vst4.16">;
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def VST4LNd32 : VST4LND<"vst4.32">;
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}
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} // mayStore = 1, hasExtraSrcRegAllocReq = 1
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//===----------------------------------------------------------------------===//
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@ -2550,6 +2552,7 @@ def VTBL1
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(ins DPR:$tbl1, DPR:$src), IIC_VTB1,
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"vtbl.8\t$dst, \\{$tbl1\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl1 DPR:$tbl1, DPR:$src)))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VTBL2
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: N3V<1,1,0b11,0b1001,0,0, (outs DPR:$dst),
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(ins DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTB2,
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@ -2568,6 +2571,7 @@ def VTBL4
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"vtbl.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbl4 DPR:$tbl1, DPR:$tbl2,
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DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
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} // hasExtraSrcRegAllocReq = 1
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// VTBX : Vector Table Extension
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def VTBX1
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@ -2576,6 +2580,7 @@ def VTBX1
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"vtbx.8\t$dst, \\{$tbl1\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx1
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DPR:$orig, DPR:$tbl1, DPR:$src)))]>;
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let hasExtraSrcRegAllocReq = 1 in {
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def VTBX2
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: N3V<1,1,0b11,0b1001,1,0, (outs DPR:$dst),
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(ins DPR:$orig, DPR:$tbl1, DPR:$tbl2, DPR:$src), IIC_VTBX2,
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@ -2594,6 +2599,7 @@ def VTBX4
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"vtbx.8\t$dst, \\{$tbl1,$tbl2,$tbl3,$tbl4\\}, $src", "$orig = $dst",
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[(set DPR:$dst, (v8i8 (int_arm_neon_vtbx4 DPR:$orig, DPR:$tbl1,
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DPR:$tbl2, DPR:$tbl3, DPR:$tbl4, DPR:$src)))]>;
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} // hasExtraSrcRegAllocReq = 1
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//===----------------------------------------------------------------------===//
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// NEON instructions for single-precision FP math
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@ -181,7 +181,8 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
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"pop${p} $wb", []>;
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@ -348,23 +349,23 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
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//
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// These requires base address to be written back or one of the loaded regs.
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let mayLoad = 1 in
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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def tLDM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iLoadm,
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"ldm${addr:submode}${p} $addr, $wb", []>;
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let mayStore = 1 in
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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def tSTM : T1I<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iStorem,
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"stm${addr:submode}${p} $addr, $wb", []>;
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let mayLoad = 1, Uses = [SP], Defs = [SP] in
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let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
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def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
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"pop${p} $wb", []>;
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let mayStore = 1, Uses = [SP], Defs = [SP] in
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let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
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def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
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"push${p} $wb", []>;
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@ -461,7 +461,7 @@ defm t2LDRB : T2I_ld<"ldrb", UnOpFrag<(zextloadi8 node:$Src)>>;
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defm t2LDRSH : T2I_ld<"ldrsh", UnOpFrag<(sextloadi16 node:$Src)>>;
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defm t2LDRSB : T2I_ld<"ldrsb", UnOpFrag<(sextloadi8 node:$Src)>>;
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let mayLoad = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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// Load doubleword
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def t2LDRDi8 : T2Ii8s4<(outs GPR:$dst1, GPR:$dst2),
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(ins t2addrmode_imm8s4:$addr),
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@ -576,7 +576,7 @@ defm t2STRB : T2I_st<"strb", BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
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defm t2STRH : T2I_st<"strh", BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
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// Store doubleword
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let mayLoad = 1 in
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let mayLoad = 1, hasExtraSrcRegAllocReq = 1 in
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def t2STRDi8 : T2Ii8s4<(outs),
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(ins GPR:$src1, GPR:$src2, t2addrmode_imm8s4:$addr),
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IIC_iStorer, "strd", " $src1, $addr", []>;
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@ -631,12 +631,12 @@ def t2STRB_POST : T2Iidxldst<(outs GPR:$base_wb),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1 in
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
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def t2LDM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iLoadm, "ldm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
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let mayStore = 1 in
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
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def t2STM : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_iStorem, "stm${addr:submode}${p}${addr:wide} $addr, $wb", []>;
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@ -1072,7 +1072,8 @@ let Defs =
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// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
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// operand list.
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// FIXME: Should pc be an implicit operand like PICADD, etc?
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1 in
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let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
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hasExtraDefRegAllocReq = 1 in
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def t2LDM_RET : T2XI<(outs),
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(ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
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IIC_Br, "ldm${addr:submode}${p}${addr:wide} $addr, $wb",
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@ -56,7 +56,7 @@ def FSTS : ASI5<0b1101, 0b00, (outs), (ins SPR:$src, addrmode5:$addr),
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// Load / store multiple Instructions.
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//
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let mayLoad = 1 in {
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let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
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def FLDMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpLoadm,
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"fldm${addr:submode}d${p} ${addr:base}, $wb",
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@ -70,9 +70,9 @@ def FLDMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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[]> {
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let Inst{20} = 1;
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}
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}
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} // mayLoad, hasExtraDefRegAllocReq
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let mayStore = 1 in {
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let mayStore = 1, hasExtraSrcRegAllocReq = 1 in {
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def FSTMD : AXDI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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variable_ops), IIC_fpStorem,
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"fstm${addr:submode}d${p} ${addr:base}, $wb",
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@ -86,7 +86,7 @@ def FSTMS : AXSI5<(outs), (ins addrmode5:$addr, pred:$p, reglist:$wb,
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[]> {
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let Inst{20} = 0;
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}
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} // mayStore
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} // mayStore, hasExtraSrcRegAllocReq
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// FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores
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