Make NumMicroOps a variable in the subtarget's instruction itinerary.

The TargetInstrInfo::getNumMicroOps API does not change, but soon it
will be used by MachineScheduler. Now each subtarget can specify the
number of micro-ops per itinerary class. For ARM, this is currently
always dynamic (-1), because it is used for load/store multiple which
depends on the number of register operands.

Zero is now a valid number of micro-ops. This can be used for
nop pseudo-instructions or instructions that the hardware can squash
during dispatch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159406 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/MC/MCInstrItineraries.h

@@ -95,7 +95,7 @@ struct InstrStage {
 /// operands are read and written.
 ///
 struct InstrItinerary {
-  unsigned NumMicroOps;        ///< # of micro-ops, 0 means it's variable
+  int      NumMicroOps;        ///< # of micro-ops, -1 means it's variable
   unsigned FirstStage;         ///< Index of first stage in itinerary
   unsigned LastStage;          ///< Index of last + 1 stage in itinerary
   unsigned FirstOperandCycle;  ///< Index of first operand rd/wr
@@ -318,11 +318,11 @@ public:
   bool isMicroCoded(unsigned ItinClassIndx) const {
     if (isEmpty())
       return false;
-    return Itineraries[ItinClassIndx].NumMicroOps != 1;
+    int UOps = Itineraries[ItinClassIndx].NumMicroOps;
+    return UOps < 0 || UOps > 1;
   }
 };
 
-
 } // End llvm namespace
 
 #endif

include/llvm/Target/TargetInstrInfo.h

@@ -648,7 +648,9 @@ public:
   }
 
   /// getNumMicroOps - Return the number of u-operations the given machine
-  /// instruction will be decoded to on the target cpu.
+  /// instruction will be decoded to on the target cpu. The itinerary's
+  /// IssueWidth is the number of microops that can be dispatched each
+  /// cycle. An instruction with zero microops takes no dispatch resources.
   virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
                                   const MachineInstr *MI) const = 0;
 

include/llvm/Target/TargetSchedule.td

@@ -73,20 +73,20 @@ class InstrStage<int cycles, list<FuncUnit> units,
 // across all chip sets.  Thus a new chip set can be added without modifying
 // instruction information.
 //
-// NumMicroOps represents the number of micro-operations that each instruction
-// in the class are decoded to. If the number is zero, then it means the
-// instruction can decode into variable number of micro-ops and it must be
-// determined dynamically.
-//
-class InstrItinClass<int ops = 1> {
-  int NumMicroOps = ops;
-}
+class InstrItinClass;
 def NoItinerary : InstrItinClass;
 
 //===----------------------------------------------------------------------===//
 // Instruction itinerary data - These values provide a runtime map of an
 // instruction itinerary class (name) to its itinerary data.
 //
+// NumMicroOps represents the number of micro-operations that each instruction
+// in the class are decoded to. If the number is zero, then it means the
+// instruction can decode into variable number of micro-ops and it must be
+// determined dynamically. This directly relates to the itineraries
+// global IssueWidth property, which constrains the number of microops
+// that can issue per cycle.
+//
 // OperandCycles are optional "cycle counts". They specify the cycle after
 // instruction issue the values which correspond to specific operand indices
 // are defined or read. Bypasses are optional "pipeline forwarding pathes", if
@@ -106,8 +106,9 @@ def NoItinerary : InstrItinClass;
 // is reduced by 1.
 class InstrItinData<InstrItinClass Class, list<InstrStage> stages,
                     list<int> operandcycles = [],
-                    list<Bypass> bypasses = []> {
+                    list<Bypass> bypasses = [], int uops = 1> {
   InstrItinClass TheClass = Class;
+  int NumMicroOps = uops;
   list<InstrStage> Stages = stages;
   list<int> OperandCycles = operandcycles;
   list<Bypass> Bypasses = bypasses;