[mips] Refactor shift immediate instructions. Separate encoding information

from the rest.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170649 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/Mips64InstrInfo.td

@@ -37,10 +37,8 @@ def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
 // Shifts
 // 64-bit shift instructions.
 let DecoderNamespace = "Mips64" in {
-class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
+class shift_rotate_imm64<string opstr, SDPatternOperator OpNode = null_frag>:
-                         SDNode OpNode>:
+  shift_rotate_imm<opstr, immZExt6, shamt, CPU64Regs, OpNode>;
-  shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt6, shamt,
-                   CPU64Regs>;
 
 // Mul, Div
 class Mult64<bits<6> func, string instr_asm, InstrItinClass itin>:
@@ -109,22 +107,20 @@ def XOR64  : ArithLogicR<"xor", IIAlu, CPU64Regs, 1, xor>, ADD_FM<0, 0x26>;
 def NOR64  : LogicNOR<0x00, 0x27, "nor", CPU64Regs>;
 
 /// Shift Instructions
-def DSLL     : shift_rotate_imm64<0x38, 0x00, "dsll", shl>;
+def DSLL   : shift_rotate_imm64<"dsll", shl>, SRA_FM<0x38, 0>;
-def DSRL     : shift_rotate_imm64<0x3a, 0x00, "dsrl", srl>;
+def DSRL   : shift_rotate_imm64<"dsrl", srl>, SRA_FM<0x3a, 0>;
-def DSRA     : shift_rotate_imm64<0x3b, 0x00, "dsra", sra>;
+def DSRA   : shift_rotate_imm64<"dsra", sra>, SRA_FM<0x3b, 0>;
 def DSLLV  : shift_rotate_reg<0x14, 0x00, "dsllv", shl, CPU64Regs>;
 def DSRLV  : shift_rotate_reg<0x16, 0x00, "dsrlv", srl, CPU64Regs>;
 def DSRAV  : shift_rotate_reg<0x17, 0x00, "dsrav", sra, CPU64Regs>;
-let Pattern = []<dag> in {
+def DSLL32 : shift_rotate_imm64<"dsll32">, SRA_FM<0x3c, 0>;
-  def DSLL32   : shift_rotate_imm64<0x3c, 0x00, "dsll32", shl>;
+def DSRL32 : shift_rotate_imm64<"dsrl32">, SRA_FM<0x3e, 0>;
-  def DSRL32   : shift_rotate_imm64<0x3e, 0x00, "dsrl32", srl>;
+def DSRA32 : shift_rotate_imm64<"dsra32">, SRA_FM<0x3f, 0>;
-  def DSRA32   : shift_rotate_imm64<0x3f, 0x00, "dsra32", sra>;
-}
 }
 // Rotate Instructions
 let Predicates = [HasMips64r2, HasStdEnc],
     DecoderNamespace = "Mips64" in {
-  def DROTR    : shift_rotate_imm64<0x3a, 0x01, "drotr", rotr>;
+  def DROTR  : shift_rotate_imm64<"drotr", rotr>, SRA_FM<0x3a, 1>;
   def DROTRV : shift_rotate_reg<0x16, 0x01, "drotrv", rotr, CPU64Regs>;
 }
 

lib/Target/Mips/MipsInstrFormats.td

@@ -220,6 +220,22 @@ class ADDI_FM<bits<6> op> {
   let Inst{15-0}  = imm16;
 }
 
+class SRA_FM<bits<6> funct, bit rotate> {
+  bits<5> rd;
+  bits<5> rt;
+  bits<5> shamt;
+
+  bits<32> Inst;
+
+  let Inst{31-26} = 0;
+  let Inst{25-22} = 0;
+  let Inst{21}    = rotate;
+  let Inst{20-16} = rt;
+  let Inst{15-11} = rd;
+  let Inst{10-6}  = shamt;
+  let Inst{5-0}   = funct;
+}
+
 //===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS

lib/Target/Mips/MipsInstrInfo.td

@@ -384,19 +384,15 @@ class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
 }
 
 // Shifts
-class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
+class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
-                       SDNode OpNode, PatFrag PF, Operand ImmOpnd,
+                       RegisterClass RC, SDPatternOperator OpNode> :
-                       RegisterClass RC>:
+  InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
-  FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
+         !strconcat(opstr, "\t$rd, $rt, $shamt"),
-     !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
+         [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
-     [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
-  let rs = isRotate;
-}
 
 // 32-bit shift instructions.
-class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
+class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
-                         SDNode OpNode>:
+  shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
-  shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
 
 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
                        SDNode OpNode, RegisterClass RC>:
@@ -940,16 +936,16 @@ def XOR  : ArithLogicR<"xor", IIAlu, CPURegs, 1, xor>, ADD_FM<0, 0x26>;
 def NOR  : LogicNOR<0x00, 0x27, "nor", CPURegs>;
 
 /// Shift Instructions
-def SLL     : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
+def SLL  : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
-def SRL     : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
+def SRL  : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
-def SRA     : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
+def SRA  : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
 
 // Rotate Instructions
 let Predicates = [HasMips32r2, HasStdEnc] in {
-    def ROTR    : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
+  def ROTR  : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
   def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
 }