mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 21:29:20 +00:00
Factor out code that emits load and store instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55854 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
9c7216f984
commit
0de588fd89
@ -45,6 +45,10 @@ public:
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#include "X86GenFastISel.inc"
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private:
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bool X86FastEmitLoad(MVT VT, unsigned Op0, Value *V, unsigned &RR);
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bool X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V);
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bool X86SelectConstAddr(Value *V, unsigned &Op0);
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bool X86SelectLoad(Instruction *I);
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@ -60,10 +64,133 @@ private:
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bool X86SelectShift(Instruction *I);
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bool X86SelectSelect(Instruction *I);
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unsigned TargetMaterializeConstant(Constant *C, MachineConstantPool* MCP);
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};
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/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
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/// The address is either pre-computed, i.e. Op0, or a GlobalAddress, i.e. V.
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/// Return true and the result register by reference if it is possible.
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bool X86FastISel::X86FastEmitLoad(MVT VT, unsigned Op0, Value *V,
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unsigned &ResultReg) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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ResultReg = createResultReg(RC);
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X86AddressMode AM;
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if (Op0)
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// Address is in register.
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AM.Base.Reg = Op0;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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return true;
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}
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/// X86FastEmitStore - Emit a machine instruction to store a value Op0 of
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/// type VT. The address is either pre-computed, i.e. Op1, or a GlobalAddress,
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/// i.e. V. Return true if it is possible.
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bool
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X86FastISel::X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8mr;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16mr;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32mr;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64mr;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSmr;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::ST_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDmr;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::ST_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::ST_FP80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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X86AddressMode AM;
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if (Op1)
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// Address is in register.
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AM.Base.Reg = Op1;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
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return true;
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}
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V,
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@ -122,61 +249,8 @@ bool X86FastISel::X86SelectStore(Instruction* I) {
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8mr;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16mr;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32mr;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64mr;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSmr;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::ST_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDmr;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::ST_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::ST_FP80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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X86AddressMode AM;
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if (Op1)
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// Address is in register.
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AM.Base.Reg = Op1;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
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return true;
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return X86FastEmitStore(VT, Op0, Op1, V);
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}
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/// X86SelectLoad - Select and emit code to implement load instructions.
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@ -200,67 +274,19 @@ bool X86FastISel::X86SelectLoad(Instruction *I) {
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unsigned Op0 = getRegForValue(V);
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if (Op0 == 0) {
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// Handle constant load address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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unsigned ResultReg = 0;
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if (X86FastEmitLoad(VT, Op0, V, ResultReg)) {
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UpdateValueMap(I, ResultReg);
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return true;
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}
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unsigned ResultReg = createResultReg(RC);
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X86AddressMode AM;
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if (Op0)
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// Address is in register.
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AM.Base.Reg = Op0;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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UpdateValueMap(I, ResultReg);
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return true;
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return false;
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}
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bool X86FastISel::X86SelectCmp(Instruction *I) {
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@ -621,10 +647,11 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
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unsigned ResultReg = createResultReg(RC);
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if (isa<GlobalValue>(C)) {
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// FIXME: If store value type is something we can't handle, this can result
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// in a dead stub load instruction.
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if (X86SelectConstAddr(C, ResultReg))
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return ResultReg;
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else
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return 0;
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return 0;
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}
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