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ARM: Add scheduling information for LDRLIT instructions to swift scheduling model

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These pseudo instructions are only lowered after register allocation and
are therefore still present when the machine scheduler runs.
Add a run: line to a testcase that uses the uncommon flags necessary to
actually produce a LDRLIT instruction on swift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun 2015-07-17 23:18:26 +00:00
parent 3df507cbfa
commit 0dec0e1ea5
2 changed files with 17 additions and 2 deletions
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7
lib/Target/ARM/ARMScheduleSwift.td
View File

@ -1558,6 +1558,13 @@ let SchedModel = SwiftModel in {
(instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
"PUSH", "tPUSH")>;
// LDRLIT pseudo instructions, they expand to LDR + PICADD
def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],
(instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>;
// LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle],
(instregex "LDRLIT_ga_pcrel_ldr")>;
// 4.2.26 Branch
def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }

12
test/CodeGen/Thumb2/pic-load.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=PIC
; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -mcpu=swift -mattr=+no-movt | FileCheck %s --check-prefix=CHECK --check-prefix=PIC-NOMOVT
%struct.anon = type { void ()* }
%struct.one_atexit_routine = type { %struct.anon, i32, i8* }
@ -8,7 +9,14 @@
define hidden i32 @atexit(void ()* %func) nounwind {
entry:
; CHECK-LABEL: atexit:
; CHECK: add r0, pc
; CHECK-PIC: add r0, pc
; CHECK-NOMOVT: ldr r[[REGNUM:[0-9]+]], LCPI0_0
; CHECK-NOMOVT: LPC0_0:
; CHECK-NOMOVT: add r[[REGNUM]], pc
; CHECK-NOMOVT: ldr r1, [r[[REGNUM]]
; CHECK-NOMOVT: blx _atexit_common
; CHECK-NOMOVT: LCPI0_0:
; CHECK-NOMOVT: .long L___dso_handle$non_lazy_ptr-(LPC0_0+4)
%r = alloca %struct.one_atexit_routine, align 4 ; <%struct.one_atexit_routine*> [#uses=3]
%0 = getelementptr %struct.one_atexit_routine, %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0 ; <void ()**> [#uses=1]
store void ()* %func, void ()** %0, align 4