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Reuse a bunch of cached subtargets and remove getSubtarget calls

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without a Function argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227638 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-01-30 23:24:40 +00:00
parent 24173bd03e
commit 0def30471a
22 changed files with 139 additions and 167 deletions
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62
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
View File

@ -39,11 +39,11 @@ namespace {
class AMDGPUDAGToDAGISel : public SelectionDAGISel { class AMDGPUDAGToDAGISel : public SelectionDAGISel {
// Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
// make the right decision when generating code for different targets. // make the right decision when generating code for different targets.
const AMDGPUSubtarget &Subtarget; const AMDGPUSubtarget *Subtarget;
public: public:
AMDGPUDAGToDAGISel(TargetMachine &TM); AMDGPUDAGToDAGISel(TargetMachine &TM);
virtual ~AMDGPUDAGToDAGISel(); virtual ~AMDGPUDAGToDAGISel();
bool runOnMachineFunction(MachineFunction &MF) override;
SDNode *Select(SDNode *N) override; SDNode *Select(SDNode *N) override;
const char *getPassName() const override; const char *getPassName() const override;
void PostprocessISelDAG() override; void PostprocessISelDAG() override;
@ -132,7 +132,11 @@ FunctionPass *llvm::createAMDGPUISelDag(TargetMachine &TM) {
} }
AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM) AMDGPUDAGToDAGISel::AMDGPUDAGToDAGISel(TargetMachine &TM)
: SelectionDAGISel(TM), Subtarget(TM.getSubtarget<AMDGPUSubtarget>()) { : SelectionDAGISel(TM) {}
bool AMDGPUDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
Subtarget = &static_cast<const AMDGPUSubtarget &>(MF.getSubtarget());
return SelectionDAGISel::runOnMachineFunction(MF);
} }
AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() { AMDGPUDAGToDAGISel::~AMDGPUDAGToDAGISel() {
@ -156,7 +160,7 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
switch (N->getMachineOpcode()) { switch (N->getMachineOpcode()) {
default: { default: {
const MCInstrDesc &Desc = const MCInstrDesc &Desc =
TM.getSubtargetImpl()->getInstrInfo()->get(N->getMachineOpcode()); Subtarget->getInstrInfo()->get(N->getMachineOpcode());
unsigned OpIdx = Desc.getNumDefs() + OpNo; unsigned OpIdx = Desc.getNumDefs() + OpNo;
if (OpIdx >= Desc.getNumOperands()) if (OpIdx >= Desc.getNumOperands())
return nullptr; return nullptr;
@ -164,17 +168,17 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
if (RegClass == -1) if (RegClass == -1)
return nullptr; return nullptr;
return TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RegClass); return Subtarget->getRegisterInfo()->getRegClass(RegClass);
} }
case AMDGPU::REG_SEQUENCE: { case AMDGPU::REG_SEQUENCE: {
unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
const TargetRegisterClass *SuperRC = const TargetRegisterClass *SuperRC =
TM.getSubtargetImpl()->getRegisterInfo()->getRegClass(RCID); Subtarget->getRegisterInfo()->getRegClass(RCID);
SDValue SubRegOp = N->getOperand(OpNo + 1); SDValue SubRegOp = N->getOperand(OpNo + 1);
unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue(); unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
return TM.getSubtargetImpl()->getRegisterInfo()->getSubClassWithSubReg( return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
SuperRC, SubRegIdx); SubRegIdx);
} }
} }
} }
@ -244,7 +248,6 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
return nullptr; // Already selected. return nullptr; // Already selected.
} }
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
switch (Opc) { switch (Opc) {
default: break; default: break;
// We are selecting i64 ADD here instead of custom lower it during // We are selecting i64 ADD here instead of custom lower it during
@ -253,7 +256,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case ISD::ADD: case ISD::ADD:
case ISD::SUB: { case ISD::SUB: {
if (N->getValueType(0) != MVT::i64 || if (N->getValueType(0) != MVT::i64 ||
ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
break; break;
return SelectADD_SUB_I64(N); return SelectADD_SUB_I64(N);
@ -262,15 +265,12 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case AMDGPUISD::BUILD_VERTICAL_VECTOR: case AMDGPUISD::BUILD_VERTICAL_VECTOR:
case ISD::BUILD_VECTOR: { case ISD::BUILD_VECTOR: {
unsigned RegClassID; unsigned RegClassID;
const AMDGPURegisterInfo *TRI = static_cast<const AMDGPURegisterInfo *>( const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
TM.getSubtargetImpl()->getRegisterInfo());
const SIRegisterInfo *SIRI = static_cast<const SIRegisterInfo *>(
TM.getSubtargetImpl()->getRegisterInfo());
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements(); unsigned NumVectorElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
assert(EltVT.bitsEq(MVT::i32)); assert(EltVT.bitsEq(MVT::i32));
if (ST.getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) { if (Subtarget->getGeneration() >= AMDGPUSubtarget::SOUTHERN_ISLANDS) {
bool UseVReg = true; bool UseVReg = true;
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end(); for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
U != E; ++U) { U != E; ++U) {
@ -281,7 +281,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
if (!RC) { if (!RC) {
continue; continue;
} }
if (SIRI->isSGPRClass(RC)) { if (static_cast<const SIRegisterInfo *>(TRI)->isSGPRClass(RC)) {
UseVReg = false; UseVReg = false;
} }
} }
@ -368,7 +368,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
} }
case ISD::BUILD_PAIR: { case ISD::BUILD_PAIR: {
SDValue RC, SubReg0, SubReg1; SDValue RC, SubReg0, SubReg1;
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
break; break;
} }
if (N->getValueType(0) == MVT::i128) { if (N->getValueType(0) == MVT::i128) {
@ -390,8 +390,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case ISD::Constant: case ISD::Constant:
case ISD::ConstantFP: { case ISD::ConstantFP: {
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>(); if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N)) N->getValueType(0).getSizeInBits() != 64 || isInlineImmediate(N))
break; break;
@ -440,7 +439,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
} }
case AMDGPUISD::REGISTER_LOAD: { case AMDGPUISD::REGISTER_LOAD: {
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
break; break;
SDValue Addr, Offset; SDValue Addr, Offset;
@ -456,7 +455,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
Ops); Ops);
} }
case AMDGPUISD::REGISTER_STORE: { case AMDGPUISD::REGISTER_STORE: {
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) if (Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
break; break;
SDValue Addr, Offset; SDValue Addr, Offset;
SelectADDRIndirect(N->getOperand(2), Addr, Offset); SelectADDRIndirect(N->getOperand(2), Addr, Offset);
@ -474,7 +473,7 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case AMDGPUISD::BFE_I32: case AMDGPUISD::BFE_I32:
case AMDGPUISD::BFE_U32: { case AMDGPUISD::BFE_U32: {
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS)
break; break;
// There is a scalar version available, but unlike the vector version which // There is a scalar version available, but unlike the vector version which
@ -579,13 +578,11 @@ bool AMDGPUDAGToDAGISel::isConstantLoad(const LoadSDNode *N, int CbId) const {
} }
bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const { bool AMDGPUDAGToDAGISel::isGlobalLoad(const LoadSDNode *N) const {
if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) { if (N->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS)
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>(); if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS ||
if (ST.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS || N->getMemoryVT().bitsLT(MVT::i32))
N->getMemoryVT().bitsLT(MVT::i32)) {
return true; return true;
}
}
return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS); return checkType(N->getMemOperand()->getValue(), AMDGPUAS::GLOBAL_ADDRESS);
} }
@ -788,12 +785,11 @@ SDNode *AMDGPUDAGToDAGISel::SelectDIV_SCALE(SDNode *N) {
bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset, bool AMDGPUDAGToDAGISel::isDSOffsetLegal(const SDValue &Base, unsigned Offset,
unsigned OffsetBits) const { unsigned OffsetBits) const {
const AMDGPUSubtarget &ST = TM.getSubtarget<AMDGPUSubtarget>();
if ((OffsetBits == 16 && !isUInt<16>(Offset)) || if ((OffsetBits == 16 && !isUInt<16>(Offset)) ||
(OffsetBits == 8 && !isUInt<8>(Offset))) (OffsetBits == 8 && !isUInt<8>(Offset)))
return false; return false;
if (ST.getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS)
return true; return true;
// On Southern Islands instruction with a negative base value and an offset // On Southern Islands instruction with a negative base value and an offset
@ -979,7 +975,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFScratch(SDValue Addr, SDValue &Rsrc,
SDLoc DL(Addr); SDLoc DL(Addr);
MachineFunction &MF = CurDAG->getMachineFunction(); MachineFunction &MF = CurDAG->getMachineFunction();
const SIRegisterInfo *TRI = const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
MachineRegisterInfo &MRI = MF.getRegInfo(); MachineRegisterInfo &MRI = MF.getRegInfo();
const SITargetLowering& Lowering = const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering()); *static_cast<const SITargetLowering*>(getTargetLowering());
@ -1033,7 +1029,7 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
SDValue &TFE) const { SDValue &TFE) const {
SDValue Ptr, VAddr, Offen, Idxen, Addr64; SDValue Ptr, VAddr, Offen, Idxen, Addr64;
const SIInstrInfo *TII = const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(Subtarget.getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64, SelectMUBUF(Addr, Ptr, VAddr, SOffset, Offset, Offen, Idxen, Addr64,
GLC, SLC, TFE); GLC, SLC, TFE);
@ -1067,7 +1063,7 @@ SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N); AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
SDLoc DL(N); SDLoc DL(N);
assert(Subtarget.hasFlatAddressSpace() && assert(Subtarget->hasFlatAddressSpace() &&
"addrspacecast only supported with flat address space!"); "addrspacecast only supported with flat address space!");
assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS && assert((ASC->getSrcAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&

11
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -102,11 +102,9 @@ EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32); return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
} }
AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,
TargetLowering(TM) { const AMDGPUSubtarget &STI)
: TargetLowering(TM), Subtarget(&STI) {
Subtarget = &TM.getSubtarget<AMDGPUSubtarget>();
setOperationAction(ISD::Constant, MVT::i32, Legal); setOperationAction(ISD::Constant, MVT::i32, Legal);
setOperationAction(ISD::Constant, MVT::i64, Legal); setOperationAction(ISD::Constant, MVT::i64, Legal);
setOperationAction(ISD::ConstantFP, MVT::f32, Legal); setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
@ -860,8 +858,7 @@ SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>( const AMDGPUFrameLowering *TFL = Subtarget->getFrameLowering();
getTargetMachine().getSubtargetImpl()->getFrameLowering());
FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op); FrameIndexSDNode *FIN = cast<FrameIndexSDNode>(Op);

2
lib/Target/R600/AMDGPUISelLowering.h
View File

@ -110,7 +110,7 @@ protected:
const SmallVectorImpl<ISD::InputArg> &Ins) const; const SmallVectorImpl<ISD::InputArg> &Ins) const;
public: public:
AMDGPUTargetLowering(TargetMachine &TM); AMDGPUTargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
bool isFAbsFree(EVT VT) const override; bool isFAbsFree(EVT VT) const override;
bool isFNegFree(EVT VT) const override; bool isFNegFree(EVT VT) const override;

5
lib/Target/R600/AMDGPUInstrInfo.cpp
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@ -319,10 +319,7 @@ int AMDGPUInstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const {
return -1; return -1;
} }
Offset = MF.getTarget() Offset = MF.getSubtarget().getFrameLowering()->getFrameIndexOffset(MF, -1);
.getSubtargetImpl()
->getFrameLowering()
->getFrameIndexOffset(MF, -1);
return getIndirectIndexBegin(MF) + Offset; return getIndirectIndexBegin(MF) + Offset;
} }

11
lib/Target/R600/AMDGPUMCInstLower.cpp
View File

@ -93,11 +93,12 @@ void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) { void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
AMDGPUMCInstLower MCInstLowering(OutContext, AMDGPUMCInstLower MCInstLowering(OutContext,
MF->getTarget().getSubtarget<AMDGPUSubtarget>()); MF->getSubtarget<AMDGPUSubtarget>());
#ifdef _DEBUG #ifdef _DEBUG
StringRef Err; StringRef Err;
if (!TM.getSubtargetImpl()->getInstrInfo()->verifyInstruction(MI, Err)) { if (!MF->getSubtarget<AMDGPUSubtarget>().getInstrInfo()->verifyInstruction(
MI, Err)) {
errs() << "Warning: Illegal instruction detected: " << Err << "\n"; errs() << "Warning: Illegal instruction detected: " << Err << "\n";
MI->dump(); MI->dump();
} }
@ -122,8 +123,8 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
raw_string_ostream DisasmStream(DisasmLine); raw_string_ostream DisasmStream(DisasmLine);
AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(),
*TM.getSubtargetImpl()->getInstrInfo(), *MF->getSubtarget().getInstrInfo(),
*TM.getSubtargetImpl()->getRegisterInfo()); *MF->getSubtarget().getRegisterInfo());
InstPrinter.printInst(&TmpInst, DisasmStream, StringRef()); InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
// Disassemble instruction/operands to hex representation. // Disassemble instruction/operands to hex representation.
@ -134,7 +135,7 @@ void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer; MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter(); MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups, InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
TM.getSubtarget<MCSubtargetInfo>()); MF->getSubtarget<MCSubtargetInfo>());
CodeStream.flush(); CodeStream.flush();
HexLines.resize(HexLines.size() + 1); HexLines.resize(HexLines.size() + 1);

4
lib/Target/R600/AMDGPUSubtarget.cpp
View File

@ -81,10 +81,10 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) { if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
InstrInfo.reset(new R600InstrInfo(*this)); InstrInfo.reset(new R600InstrInfo(*this));
TLInfo.reset(new R600TargetLowering(TM)); TLInfo.reset(new R600TargetLowering(TM, *this));
} else { } else {
InstrInfo.reset(new SIInstrInfo(*this)); InstrInfo.reset(new SIInstrInfo(*this));
TLInfo.reset(new SITargetLowering(TM)); TLInfo.reset(new SITargetLowering(TM, *this));
} }
} }

4
lib/Target/R600/CIInstructions.td
View File

@ -11,8 +11,8 @@
def isCIVI : Predicate < def isCIVI : Predicate <
"Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || " "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS || "
"Subtarget.getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS" "Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS"
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

2
lib/Target/R600/CaymanInstructions.td
View File

@ -12,7 +12,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def isCayman : Predicate<"Subtarget.hasCaymanISA()">; def isCayman : Predicate<"Subtarget->hasCaymanISA()">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Cayman Instructions // Cayman Instructions

10
lib/Target/R600/EvergreenInstructions.td
View File

@ -14,14 +14,14 @@
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def isEG : Predicate< def isEG : Predicate<
"Subtarget.getGeneration() >= AMDGPUSubtarget::EVERGREEN && " "Subtarget->getGeneration() >= AMDGPUSubtarget::EVERGREEN && "
"Subtarget.getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && " "Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS && "
"!Subtarget.hasCaymanISA()" "!Subtarget->hasCaymanISA()"
>; >;
def isEGorCayman : Predicate< def isEGorCayman : Predicate<
"Subtarget.getGeneration() == AMDGPUSubtarget::EVERGREEN ||" "Subtarget->getGeneration() == AMDGPUSubtarget::EVERGREEN ||"
"Subtarget.getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS" "Subtarget->getGeneration() ==AMDGPUSubtarget::NORTHERN_ISLANDS"
>; >;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

46
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -39,14 +39,14 @@ struct CFStack {
FIRST_NON_WQM_PUSH_W_FULL_ENTRY = 3 FIRST_NON_WQM_PUSH_W_FULL_ENTRY = 3
}; };
const AMDGPUSubtarget &ST; const AMDGPUSubtarget *ST;
std::vector<StackItem> BranchStack; std::vector<StackItem> BranchStack;
std::vector<StackItem> LoopStack; std::vector<StackItem> LoopStack;
unsigned MaxStackSize; unsigned MaxStackSize;
unsigned CurrentEntries; unsigned CurrentEntries;
unsigned CurrentSubEntries; unsigned CurrentSubEntries;
CFStack(const AMDGPUSubtarget &st, unsigned ShaderType) : ST(st), CFStack(const AMDGPUSubtarget *st, unsigned ShaderType) : ST(st),
// We need to reserve a stack entry for CALL_FS in vertex shaders. // We need to reserve a stack entry for CALL_FS in vertex shaders.
MaxStackSize(ShaderType == ShaderType::VERTEX ? 1 : 0), MaxStackSize(ShaderType == ShaderType::VERTEX ? 1 : 0),
CurrentEntries(0), CurrentSubEntries(0) { } CurrentEntries(0), CurrentSubEntries(0) { }
@ -76,11 +76,11 @@ bool CFStack::branchStackContains(CFStack::StackItem Item) {
} }
bool CFStack::requiresWorkAroundForInst(unsigned Opcode) { bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST.hasCaymanISA() && if (Opcode == AMDGPU::CF_ALU_PUSH_BEFORE && ST->hasCaymanISA() &&
getLoopDepth() > 1) getLoopDepth() > 1)
return true; return true;
if (!ST.hasCFAluBug()) if (!ST->hasCFAluBug())
return false; return false;
switch(Opcode) { switch(Opcode) {
@ -91,7 +91,7 @@ bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
case AMDGPU::CF_ALU_CONTINUE: case AMDGPU::CF_ALU_CONTINUE:
if (CurrentSubEntries == 0) if (CurrentSubEntries == 0)
return false; return false;
if (ST.getWavefrontSize() == 64) { if (ST->getWavefrontSize() == 64) {
// We are being conservative here. We only require this work-around if // We are being conservative here. We only require this work-around if
// CurrentSubEntries > 3 && // CurrentSubEntries > 3 &&
// (CurrentSubEntries % 4 == 3 || CurrentSubEntries % 4 == 0) // (CurrentSubEntries % 4 == 3 || CurrentSubEntries % 4 == 0)
@ -102,7 +102,7 @@ bool CFStack::requiresWorkAroundForInst(unsigned Opcode) {
// resources without any problems. // resources without any problems.
return CurrentSubEntries > 3; return CurrentSubEntries > 3;
} else { } else {
assert(ST.getWavefrontSize() == 32); assert(ST->getWavefrontSize() == 32);
// We are being conservative here. We only require the work-around if // We are being conservative here. We only require the work-around if
// CurrentSubEntries > 7 && // CurrentSubEntries > 7 &&
// (CurrentSubEntries % 8 == 7 || CurrentSubEntries % 8 == 0) // (CurrentSubEntries % 8 == 7 || CurrentSubEntries % 8 == 0)
@ -118,8 +118,8 @@ unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
default: default:
return 0; return 0;
case CFStack::FIRST_NON_WQM_PUSH: case CFStack::FIRST_NON_WQM_PUSH:
assert(!ST.hasCaymanISA()); assert(!ST->hasCaymanISA());
if (ST.getGeneration() <= AMDGPUSubtarget::R700) { if (ST->getGeneration() <= AMDGPUSubtarget::R700) {
// +1 For the push operation. // +1 For the push operation.
// +2 Extra space required. // +2 Extra space required.
return 3; return 3;
@ -132,7 +132,7 @@ unsigned CFStack::getSubEntrySize(CFStack::StackItem Item) {
return 2; return 2;
} }
case CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY: case CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY:
assert(ST.getGeneration() >= AMDGPUSubtarget::EVERGREEN); assert(ST->getGeneration() >= AMDGPUSubtarget::EVERGREEN);
// +1 For the push operation. // +1 For the push operation.
// +1 Extra space required. // +1 Extra space required.
return 2; return 2;
@ -153,13 +153,14 @@ void CFStack::pushBranch(unsigned Opcode, bool isWQM) {
case AMDGPU::CF_PUSH_EG: case AMDGPU::CF_PUSH_EG:
case AMDGPU::CF_ALU_PUSH_BEFORE: case AMDGPU::CF_ALU_PUSH_BEFORE:
if (!isWQM) { if (!isWQM) {
if (!ST.hasCaymanISA() && !branchStackContains(CFStack::FIRST_NON_WQM_PUSH)) if (!ST->hasCaymanISA() &&
!branchStackContains(CFStack::FIRST_NON_WQM_PUSH))
Item = CFStack::FIRST_NON_WQM_PUSH; // May not be required on Evergreen/NI Item = CFStack::FIRST_NON_WQM_PUSH; // May not be required on Evergreen/NI
// See comment in // See comment in
// CFStack::getSubEntrySize() // CFStack::getSubEntrySize()
else if (CurrentEntries > 0 && else if (CurrentEntries > 0 &&
ST.getGeneration() > AMDGPUSubtarget::EVERGREEN && ST->getGeneration() > AMDGPUSubtarget::EVERGREEN &&
!ST.hasCaymanISA() && !ST->hasCaymanISA() &&
!branchStackContains(CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY)) !branchStackContains(CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY))
Item = CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY; Item = CFStack::FIRST_NON_WQM_PUSH_W_FULL_ENTRY;
else else
@ -219,7 +220,7 @@ private:
const R600InstrInfo *TII; const R600InstrInfo *TII;
const R600RegisterInfo *TRI; const R600RegisterInfo *TRI;
unsigned MaxFetchInst; unsigned MaxFetchInst;
const AMDGPUSubtarget &ST; const AMDGPUSubtarget *ST;
bool IsTrivialInst(MachineInstr *MI) const { bool IsTrivialInst(MachineInstr *MI) const {
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
@ -233,7 +234,7 @@ private:
const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const { const MCInstrDesc &getHWInstrDesc(ControlFlowInstruction CFI) const {
unsigned Opcode = 0; unsigned Opcode = 0;
bool isEg = (ST.getGeneration() >= AMDGPUSubtarget::EVERGREEN); bool isEg = (ST->getGeneration() >= AMDGPUSubtarget::EVERGREEN);
switch (CFI) { switch (CFI) {
case CF_TC: case CF_TC:
Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600; Opcode = isEg ? AMDGPU::CF_TC_EG : AMDGPU::CF_TC_R600;
@ -266,7 +267,7 @@ private:
Opcode = isEg ? AMDGPU::POP_EG : AMDGPU::POP_R600; Opcode = isEg ? AMDGPU::POP_EG : AMDGPU::POP_R600;
break; break;
case CF_END: case CF_END:
if (ST.hasCaymanISA()) { if (ST->hasCaymanISA()) {
Opcode = AMDGPU::CF_END_CM; Opcode = AMDGPU::CF_END_CM;
break; break;
} }
@ -467,17 +468,14 @@ private:
} }
public: public:
R600ControlFlowFinalizer(TargetMachine &tm) : MachineFunctionPass(ID), R600ControlFlowFinalizer(TargetMachine &tm)
TII (nullptr), TRI(nullptr), : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr), ST(nullptr) {}
ST(tm.getSubtarget<AMDGPUSubtarget>()) {
const AMDGPUSubtarget &ST = tm.getSubtarget<AMDGPUSubtarget>();
MaxFetchInst = ST.getTexVTXClauseSize();
}
bool runOnMachineFunction(MachineFunction &MF) override { bool runOnMachineFunction(MachineFunction &MF) override {
TII = static_cast<const R600InstrInfo *>(MF.getSubtarget().getInstrInfo()); ST = &MF.getSubtarget<AMDGPUSubtarget>();
TRI = static_cast<const R600RegisterInfo *>( MaxFetchInst = ST->getTexVTXClauseSize();
MF.getSubtarget().getRegisterInfo()); TII = static_cast<const R600InstrInfo *>(ST->getInstrInfo());
TRI = static_cast<const R600RegisterInfo *>(ST->getRegisterInfo());
R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>(); R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
CFStack CFStack(ST, MFI->getShaderType()); CFStack CFStack(ST, MFI->getShaderType());

21
lib/Target/R600/R600ISelLowering.cpp
View File

@ -30,9 +30,9 @@
using namespace llvm; using namespace llvm;
R600TargetLowering::R600TargetLowering(TargetMachine &TM) : R600TargetLowering::R600TargetLowering(TargetMachine &TM,
AMDGPUTargetLowering(TM), const AMDGPUSubtarget &STI)
Gen(TM.getSubtarget<AMDGPUSubtarget>().getGeneration()) { : AMDGPUTargetLowering(TM, STI), Gen(STI.getGeneration()) {
addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass); addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass); addRegisterClass(MVT::f32, &AMDGPU::R600_Reg32RegClass);
addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass); addRegisterClass(MVT::v4i32, &AMDGPU::R600_Reg128RegClass);
@ -197,7 +197,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
MachineRegisterInfo &MRI = MF->getRegInfo(); MachineRegisterInfo &MRI = MF->getRegInfo();
MachineBasicBlock::iterator I = *MI; MachineBasicBlock::iterator I = *MI;
const R600InstrInfo *TII = const R600InstrInfo *TII =
static_cast<const R600InstrInfo *>(MF->getSubtarget().getInstrInfo()); static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: default:
@ -652,9 +652,8 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue(); int ijb = cast<ConstantSDNode>(Op.getOperand(2))->getSExtValue();
MachineSDNode *interp; MachineSDNode *interp;
if (ijb < 0) { if (ijb < 0) {
const MachineFunction &MF = DAG.getMachineFunction(); const R600InstrInfo *TII =
const R600InstrInfo *TII = static_cast<const R600InstrInfo *>( static_cast<const R600InstrInfo *>(Subtarget->getInstrInfo());
MF.getSubtarget().getInstrInfo());
interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL, interp = DAG.getMachineNode(AMDGPU::INTERP_VEC_LOAD, DL,
MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32)); MVT::v4f32, DAG.getTargetConstant(slot / 4 , MVT::i32));
return DAG.getTargetExtractSubreg( return DAG.getTargetExtractSubreg(
@ -1381,8 +1380,8 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
// Lowering for indirect addressing // Lowering for indirect addressing
const MachineFunction &MF = DAG.getMachineFunction(); const MachineFunction &MF = DAG.getMachineFunction();
const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>( const AMDGPUFrameLowering *TFL =
getTargetMachine().getSubtargetImpl()->getFrameLowering()); static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
unsigned StackWidth = TFL->getStackWidth(MF); unsigned StackWidth = TFL->getStackWidth(MF);
Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG); Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);
@ -1579,8 +1578,8 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
// Lowering for indirect addressing // Lowering for indirect addressing
const MachineFunction &MF = DAG.getMachineFunction(); const MachineFunction &MF = DAG.getMachineFunction();
const AMDGPUFrameLowering *TFL = static_cast<const AMDGPUFrameLowering *>( const AMDGPUFrameLowering *TFL =
getTargetMachine().getSubtargetImpl()->getFrameLowering()); static_cast<const AMDGPUFrameLowering *>(Subtarget->getFrameLowering());
unsigned StackWidth = TFL->getStackWidth(MF); unsigned StackWidth = TFL->getStackWidth(MF);
Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG); Ptr = stackPtrToRegIndex(Ptr, StackWidth, DAG);

2
lib/Target/R600/R600ISelLowering.h
View File

@ -23,7 +23,7 @@ class R600InstrInfo;
class R600TargetLowering : public AMDGPUTargetLowering { class R600TargetLowering : public AMDGPUTargetLowering {
public: public:
R600TargetLowering(TargetMachine &TM); R600TargetLowering(TargetMachine &TM, const AMDGPUSubtarget &STI);
MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock * BB) const override; MachineBasicBlock * BB) const override;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;

7
lib/Target/R600/R600Instructions.td
View File

@ -335,10 +335,11 @@ def load_param : LoadParamFrag<load>;
def load_param_exti8 : LoadParamFrag<az_extloadi8>; def load_param_exti8 : LoadParamFrag<az_extloadi8>;
def load_param_exti16 : LoadParamFrag<az_extloadi16>; def load_param_exti16 : LoadParamFrag<az_extloadi16>;
def isR600 : Predicate<"Subtarget.getGeneration() <= AMDGPUSubtarget::R700">; def isR600 : Predicate<"Subtarget->getGeneration() <= AMDGPUSubtarget::R700">;
def isR600toCayman : Predicate< def isR600toCayman
"Subtarget.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">; : Predicate<
"Subtarget->getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// R600 SDNodes // R600 SDNodes

5
lib/Target/R600/R600MachineScheduler.cpp
View File

@ -26,17 +26,16 @@ using namespace llvm;
void R600SchedStrategy::initialize(ScheduleDAGMI *dag) { void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness");
DAG = static_cast<ScheduleDAGMILive*>(dag); DAG = static_cast<ScheduleDAGMILive*>(dag);
const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
TII = static_cast<const R600InstrInfo*>(DAG->TII); TII = static_cast<const R600InstrInfo*>(DAG->TII);
TRI = static_cast<const R600RegisterInfo*>(DAG->TRI); TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
VLIW5 = !DAG->MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA(); VLIW5 = !ST.hasCaymanISA();
MRI = &DAG->MRI; MRI = &DAG->MRI;
CurInstKind = IDOther; CurInstKind = IDOther;
CurEmitted = 0; CurEmitted = 0;
OccupedSlotsMask = 31; OccupedSlotsMask = 31;
InstKindLimit[IDAlu] = TII->getMaxAlusPerClause(); InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
InstKindLimit[IDOther] = 32; InstKindLimit[IDOther] = 32;
const AMDGPUSubtarget &ST = DAG->TM.getSubtarget<AMDGPUSubtarget>();
InstKindLimit[IDFetch] = ST.getTexVTXClauseSize(); InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
AluInstCount = 0; AluInstCount = 0;
FetchInstCount = 0; FetchInstCount = 0;

2
lib/Target/R600/R600Packetizer.cpp
View File

@ -153,7 +153,7 @@ public:
TII(static_cast<const R600InstrInfo *>( TII(static_cast<const R600InstrInfo *>(
MF.getSubtarget().getInstrInfo())), MF.getSubtarget().getInstrInfo())),
TRI(TII->getRegisterInfo()) { TRI(TII->getRegisterInfo()) {
VLIW5 = !MF.getTarget().getSubtarget<AMDGPUSubtarget>().hasCaymanISA(); VLIW5 = !MF.getSubtarget<AMDGPUSubtarget>().hasCaymanISA();
} }
// initPacketizerState - initialize some internal flags. // initPacketizerState - initialize some internal flags.

2
lib/Target/R600/R700Instructions.td
View File

@ -13,7 +13,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">; def isR700 : Predicate<"Subtarget->getGeneration() == AMDGPUSubtarget::R700">;
let Predicates = [isR700] in { let Predicates = [isR700] in {
def SIN_r700 : SIN_Common<0x6E>; def SIN_r700 : SIN_Common<0x6E>;

64
lib/Target/R600/SIISelLowering.cpp
View File

@ -35,8 +35,9 @@
using namespace llvm; using namespace llvm;
SITargetLowering::SITargetLowering(TargetMachine &TM) : SITargetLowering::SITargetLowering(TargetMachine &TM,
AMDGPUTargetLowering(TM) { const AMDGPUSubtarget &STI)
: AMDGPUTargetLowering(TM, STI) {
addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass); addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
@ -366,8 +367,8 @@ SITargetLowering::getPreferredVectorAction(EVT VT) const {
bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const { Type *Ty) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
return TII->isInlineConstant(Imm); return TII->isInlineConstant(Imm);
} }
@ -400,16 +401,11 @@ SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
} }
SDValue SITargetLowering::LowerFormalArguments( SDValue SITargetLowering::LowerFormalArguments(
SDValue Chain, SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
CallingConv::ID CallConv, const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
bool isVarArg, SmallVectorImpl<SDValue> &InVals) const {
const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc DL, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const {
const TargetMachine &TM = getTargetMachine();
const SIRegisterInfo *TRI = const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo()); static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
FunctionType *FType = MF.getFunction()->getFunctionType(); FunctionType *FType = MF.getFunction()->getFunctionType();
@ -601,8 +597,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
MachineInstr * MI, MachineBasicBlock * BB) const { MachineInstr * MI, MachineBasicBlock * BB) const {
MachineBasicBlock::iterator I = *MI; MachineBasicBlock::iterator I = *MI;
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
switch (MI->getOpcode()) { switch (MI->getOpcode()) {
default: default:
@ -864,7 +860,7 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
const SIRegisterInfo *TRI = const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo*>(MF.getSubtarget().getRegisterInfo()); static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
SDLoc DL(Op); SDLoc DL(Op);
@ -1335,8 +1331,8 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
if (!CAdd) if (!CAdd)
return SDValue(); return SDValue();
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
// If the resulting offset is too large, we can't fold it into the addressing // If the resulting offset is too large, we can't fold it into the addressing
// mode offset. // mode offset.
@ -1738,8 +1734,8 @@ static bool isVSrc(unsigned RegClass) {
/// and the immediate value if it's a literal immediate /// and the immediate value if it's a literal immediate
int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const { int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) { if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
if (Node->getZExtValue() >> 32) if (Node->getZExtValue() >> 32)
@ -1764,10 +1760,11 @@ int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
return -1; return -1;
} }
const TargetRegisterClass *SITargetLowering::getRegClassForNode( const TargetRegisterClass *
SelectionDAG &DAG, const SDValue &Op) const { SITargetLowering::getRegClassForNode(SelectionDAG &DAG,
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SDValue &Op) const {
getTargetMachine().getSubtargetImpl()->getInstrInfo()); const SIInstrInfo *TII =
static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
const SIRegisterInfo &TRI = TII->getRegisterInfo(); const SIRegisterInfo &TRI = TII->getRegisterInfo();
if (!Op->isMachineOpcode()) { if (!Op->isMachineOpcode()) {
@ -1818,8 +1815,7 @@ const TargetRegisterClass *SITargetLowering::getRegClassForNode(
/// \brief Does "Op" fit into register class "RegClass" ? /// \brief Does "Op" fit into register class "RegClass" ?
bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op, bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
unsigned RegClass) const { unsigned RegClass) const {
const TargetRegisterInfo *TRI = const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
getTargetMachine().getSubtargetImpl()->getRegisterInfo();
const TargetRegisterClass *RC = getRegClassForNode(DAG, Op); const TargetRegisterClass *RC = getRegClassForNode(DAG, Op);
if (!RC) { if (!RC) {
return false; return false;
@ -1943,8 +1939,8 @@ void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
/// \brief Fold the instructions after selecting them. /// \brief Fold the instructions after selecting them.
SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
SelectionDAG &DAG) const { SelectionDAG &DAG) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
Node = AdjustRegClass(Node, DAG); Node = AdjustRegClass(Node, DAG);
if (TII->isMIMG(Node->getMachineOpcode())) if (TII->isMIMG(Node->getMachineOpcode()))
@ -1962,8 +1958,8 @@ SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
/// bits set in the writemask /// bits set in the writemask
void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
SDNode *Node) const { SDNode *Node) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
TII->legalizeOperands(MI); TII->legalizeOperands(MI);
@ -2009,8 +2005,8 @@ static SDValue buildSMovImm32(SelectionDAG &DAG, SDLoc DL, uint64_t Val) {
MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG, MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
SDLoc DL, SDLoc DL,
SDValue Ptr) const { SDValue Ptr) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
#if 1 #if 1
// XXX - Workaround for moveToVALU not handling different register class // XXX - Workaround for moveToVALU not handling different register class
// inserts for REG_SEQUENCE. // inserts for REG_SEQUENCE.
@ -2091,8 +2087,8 @@ MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG,
MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG, MachineSDNode *SITargetLowering::buildScratchRSRC(SelectionDAG &DAG,
SDLoc DL, SDLoc DL,
SDValue Ptr) const { SDValue Ptr) const {
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>( const SIInstrInfo *TII =
getTargetMachine().getSubtargetImpl()->getInstrInfo()); static_cast<const SIInstrInfo *>(Subtarget->getInstrInfo());
uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE | uint64_t Rsrc = TII->getDefaultRsrcDataFormat() | AMDGPU::RSRC_TID_ENABLE |
0xffffffff; // Size 0xffffffff; // Size

2
lib/Target/R600/SIISelLowering.h
View File

@ -63,7 +63,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const; SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
public: public:
SITargetLowering(TargetMachine &tm); SITargetLowering(TargetMachine &tm, const AMDGPUSubtarget &STI);
bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/, bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
EVT /*VT*/) const override; EVT /*VT*/) const override;

5
lib/Target/R600/SIInstrInfo.cpp
View File

@ -28,8 +28,7 @@
using namespace llvm; using namespace llvm;
SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st) SIInstrInfo::SIInstrInfo(const AMDGPUSubtarget &st)
: AMDGPUInstrInfo(st), : AMDGPUInstrInfo(st), RI(st) {}
RI(st) { }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TargetInstrInfo callbacks // TargetInstrInfo callbacks
@ -539,7 +538,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
unsigned Size) const { unsigned Size) const {
MachineFunction *MF = MBB.getParent(); MachineFunction *MF = MBB.getParent();
SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>(); SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
const AMDGPUSubtarget &ST = MF->getTarget().getSubtarget<AMDGPUSubtarget>(); const AMDGPUSubtarget &ST = MF->getSubtarget<AMDGPUSubtarget>();
const SIRegisterInfo *TRI = const SIRegisterInfo *TRI =
static_cast<const SIRegisterInfo*>(ST.getRegisterInfo()); static_cast<const SIRegisterInfo*>(ST.getRegisterInfo());
DebugLoc DL = MBB.findDebugLoc(MI); DebugLoc DL = MBB.findDebugLoc(MI);

5
lib/Target/R600/SIInstrInfo.td
View File

@ -211,12 +211,11 @@ class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
}]>; }]>;
class SGPRImm <dag frag> : PatLeaf<frag, [{ class SGPRImm <dag frag> : PatLeaf<frag, [{
if (TM.getSubtarget<AMDGPUSubtarget>().getGeneration() < if (Subtarget->getGeneration() < AMDGPUSubtarget::SOUTHERN_ISLANDS) {
AMDGPUSubtarget::SOUTHERN_ISLANDS) {
return false; return false;
} }
const SIRegisterInfo *SIRI = const SIRegisterInfo *SIRI =
static_cast<const SIRegisterInfo*>(TM.getSubtargetImpl()->getRegisterInfo()); static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end(); for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
U != E; ++U) { U != E; ++U) {
if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) { if (SIRI->isSGPRClass(getOperandRegClass(*U, U.getOperandNo()))) {

10
lib/Target/R600/SIInstructions.td
View File

@ -26,16 +26,16 @@ def SendMsgImm : Operand<i32> {
let PrintMethod = "printSendMsg"; let PrintMethod = "printSendMsg";
} }
def isGCN : Predicate<"Subtarget.getGeneration() " def isGCN : Predicate<"Subtarget->getGeneration() "
">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">;
def isSICI : Predicate< def isSICI : Predicate<
"Subtarget.getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||" "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
"Subtarget.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS" "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
>; >;
def isCI : Predicate<"Subtarget.getGeneration() " def isCI : Predicate<"Subtarget->getGeneration() "
">= AMDGPUSubtarget::SEA_ISLANDS">; ">= AMDGPUSubtarget::SEA_ISLANDS">;
def isVI : Predicate < def isVI : Predicate <
"Subtarget.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS" "Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS"
>; >;
def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">; def HasFlatAddressSpace : Predicate<"Subtarget.hasFlatAddressSpace()">;

24
lib/Target/R600/SILoadStoreOptimizer.cpp
View File

@ -55,7 +55,6 @@ namespace {
class SILoadStoreOptimizer : public MachineFunctionPass { class SILoadStoreOptimizer : public MachineFunctionPass {
private: private:
const TargetMachine *TM;
const SIInstrInfo *TII; const SIInstrInfo *TII;
const SIRegisterInfo *TRI; const SIRegisterInfo *TRI;
MachineRegisterInfo *MRI; MachineRegisterInfo *MRI;
@ -86,20 +85,11 @@ private:
public: public:
static char ID; static char ID;
SILoadStoreOptimizer() : SILoadStoreOptimizer()
MachineFunctionPass(ID), : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr), MRI(nullptr),
TM(nullptr), LIS(nullptr) {}
TII(nullptr),
TRI(nullptr),
MRI(nullptr),
LIS(nullptr) {
} SILoadStoreOptimizer(const TargetMachine &TM_) : MachineFunctionPass(ID) {
SILoadStoreOptimizer(const TargetMachine &TM_) :
MachineFunctionPass(ID),
TM(&TM_),
TII(static_cast<const SIInstrInfo*>(TM->getSubtargetImpl()->getInstrInfo())) {
initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry()); initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
} }
@ -414,9 +404,9 @@ bool SILoadStoreOptimizer::optimizeBlock(MachineBasicBlock &MBB) {
} }
bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) { bool SILoadStoreOptimizer::runOnMachineFunction(MachineFunction &MF) {
const TargetSubtargetInfo *STM = MF.getTarget().getSubtargetImpl(); const TargetSubtargetInfo &STM = MF.getSubtarget();
TRI = static_cast<const SIRegisterInfo*>(STM->getRegisterInfo()); TRI = static_cast<const SIRegisterInfo *>(STM.getRegisterInfo());
TII = static_cast<const SIInstrInfo*>(STM->getInstrInfo()); TII = static_cast<const SIInstrInfo *>(STM.getInstrInfo());
MRI = &MF.getRegInfo(); MRI = &MF.getRegInfo();
LIS = &getAnalysis<LiveIntervals>(); LIS = &getAnalysis<LiveIntervals>();