mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-26 23:24:34 +00:00
Implementation of instruction scheduling for LLVM.
Currently schedules one basic block at a time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
86
include/llvm/CodeGen/InstrScheduling.h
Normal file
86
include/llvm/CodeGen/InstrScheduling.h
Normal file
@ -0,0 +1,86 @@
|
|||||||
|
// $Id$
|
||||||
|
//***************************************************************************
|
||||||
|
// File:
|
||||||
|
// InstrScheduling.h
|
||||||
|
//
|
||||||
|
// Purpose:
|
||||||
|
//
|
||||||
|
// History:
|
||||||
|
// 7/23/01 - Vikram Adve - Created
|
||||||
|
//***************************************************************************
|
||||||
|
|
||||||
|
#ifndef LLVM_CODEGEN_INSTR_SCHEDULING_H
|
||||||
|
#define LLVM_CODEGEN_INSTR_SCHEDULING_H
|
||||||
|
|
||||||
|
|
||||||
|
//************************ User Include Files *****************************/
|
||||||
|
|
||||||
|
#include "llvm/Support/CommandLine.h"
|
||||||
|
#include "llvm/CodeGen/TargetMachine.h"
|
||||||
|
|
||||||
|
//************************ Opaque Declarations*****************************/
|
||||||
|
|
||||||
|
class Method;
|
||||||
|
class SchedulingManager;
|
||||||
|
|
||||||
|
//************************ Exported Data Types *****************************/
|
||||||
|
|
||||||
|
// Debug option levels for instruction scheduling
|
||||||
|
enum SchedDebugLevel_t {
|
||||||
|
Sched_NoDebugInfo,
|
||||||
|
Sched_PrintMachineCode,
|
||||||
|
Sched_PrintSchedTrace,
|
||||||
|
Sched_PrintSchedGraphs,
|
||||||
|
};
|
||||||
|
|
||||||
|
extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
|
||||||
|
|
||||||
|
|
||||||
|
//************************** External Classes ******************************/
|
||||||
|
|
||||||
|
|
||||||
|
//************************* External Functions *****************************/
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Function: ScheduleInstructionsWithSSA
|
||||||
|
//
|
||||||
|
// Purpose:
|
||||||
|
// Entry point for instruction scheduling on SSA form.
|
||||||
|
// Schedules the machine instructions generated by instruction selection.
|
||||||
|
// Assumes that register allocation has not been done, i.e., operands
|
||||||
|
// are still in SSA form.
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
bool ScheduleInstructionsWithSSA (Method* method,
|
||||||
|
const TargetMachine &Target);
|
||||||
|
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Function: ScheduleInstructions
|
||||||
|
//
|
||||||
|
// Purpose:
|
||||||
|
// Entry point for instruction scheduling on machine code.
|
||||||
|
// Schedules the machine instructions generated by instruction selection.
|
||||||
|
// Assumes that register allocation has been done.
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// Not implemented yet.
|
||||||
|
bool ScheduleInstructions (Method* method,
|
||||||
|
const TargetMachine &Target);
|
||||||
|
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
// Function: instrIsFeasible
|
||||||
|
//
|
||||||
|
// Purpose:
|
||||||
|
// Used by the priority analysis to filter out instructions
|
||||||
|
// that are not feasible to issue in the current cycle.
|
||||||
|
// Should only be used during schedule construction..
|
||||||
|
//---------------------------------------------------------------------------
|
||||||
|
|
||||||
|
bool instrIsFeasible (const SchedulingManager& S,
|
||||||
|
MachineOpCode opCode);
|
||||||
|
|
||||||
|
//**************************************************************************/
|
||||||
|
|
||||||
|
#endif
|
1464
lib/CodeGen/InstrSched/InstrScheduling.cpp
Normal file
1464
lib/CodeGen/InstrSched/InstrScheduling.cpp
Normal file
File diff suppressed because it is too large
Load Diff
1464
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
Normal file
1464
lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user