diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 5c80f9773ed..dd65dd9fc34 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -1192,6 +1192,7 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
   // L2:
   ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImmedValue();
   CC = ARMCC::getOppositeCondition(CC);
+  unsigned CCReg = MI->getOperand(2).getReg();
 
   // If the branch is at the end of its MBB and that has a fall-through block,
   // direct the updated conditional branch to the fall-through block. Otherwise,
@@ -1241,7 +1242,8 @@ ARMConstantIslands::FixUpConditionalBr(MachineFunction &Fn, ImmBranch &Br) {
 
   // Insert a new conditional branch and a new unconditional branch.
   // Also update the ImmBranch as well as adding a new entry for the new branch.
-  BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB).addImm(CC);
+  BuildMI(MBB, TII->get(MI->getOpcode())).addMBB(NextBB)
+    .addImm(CC).addReg(CCReg);
   Br.MI = &MBB->back();
   BBSizes[MBB->getNumber()] += ARM::GetInstSize(&MBB->back());
   BuildMI(MBB, TII->get(Br.UncondBr)).addMBB(DestBB);
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index dd970954f01..6f67d66e672 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1127,8 +1127,9 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
 
   if (LHS.getValueType() == MVT::i32) {
     SDOperand ARMCC;
+    SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
     SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
-    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp);
+    return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
   }
 
   ARMCC::CondCodes CondCode, CondCode2;
@@ -1136,14 +1137,15 @@ static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
     std::swap(TrueVal, FalseVal);
 
   SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
+  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
   SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
   SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
-                                 ARMCC, Cmp);
+                                 ARMCC, CCR, Cmp);
   if (CondCode2 != ARMCC::AL) {
     SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
     // FIXME: Needs another CMP because flag can have but one use.
     SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
-    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2);
+    Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
   }
   return Result;
 }
@@ -1158,8 +1160,9 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
 
   if (LHS.getValueType() == MVT::i32) {
     SDOperand ARMCC;
+    SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
     SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
-    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp);
+    return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
   }
 
   assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
@@ -1170,13 +1173,14 @@ static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
   
   SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
   SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
+  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
   SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
-  SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp };
-  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
+  SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
+  SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
   if (CondCode2 != ARMCC::AL) {
     ARMCC = DAG.getConstant(CondCode2, MVT::i32);
-    SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) };
-    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4);
+    SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
+    Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
   }
   return Res;
 }
@@ -1228,7 +1232,8 @@ static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
   SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
   SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
   SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
-  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp);
+  SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
+  return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
 }
 
 static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) {
@@ -1472,7 +1477,7 @@ ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
     MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
     MachineBasicBlock *sinkMBB  = new MachineBasicBlock(LLVM_BB);
     BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
-      .addImm(MI->getOperand(3).getImm());
+      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
     MachineFunction *F = BB->getParent();
     F->getBasicBlockList().insert(It, copy0MBB);
     F->getBasicBlockList().insert(It, sinkMBB);
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 1370faba4d7..5af89b742e3 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -322,6 +322,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
       // Block ends with fall-through condbranch.
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       Cond.push_back(LastInst->getOperand(1));
+      Cond.push_back(LastInst->getOperand(2));
       return false;
     }
     return true;  // Can't handle indirect branch.
@@ -341,6 +342,7 @@ bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
       (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
     TBB =  SecondLastInst->getOperand(0).getMachineBasicBlock();
     Cond.push_back(SecondLastInst->getOperand(1));
+    Cond.push_back(SecondLastInst->getOperand(2));
     FBB = LastInst->getOperand(0).getMachineBasicBlock();
     return false;
   }
@@ -397,19 +399,21 @@ unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *T
 
   // Shouldn't be a fall through.
   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
-  assert((Cond.size() == 1 || Cond.size() == 0) &&
+  assert((Cond.size() == 2 || Cond.size() == 0) &&
          "ARM branch conditions have two components!");
   
   if (FBB == 0) {
     if (Cond.empty()) // Unconditional branch?
       BuildMI(&MBB, get(BOpc)).addMBB(TBB);
     else
-      BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
+      BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
+        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
     return 1;
   }
   
   // Two-way conditional branch.
-  BuildMI(&MBB, get(BccOpc)).addMBB(TBB).addImm(Cond[0].getImm());
+  BuildMI(&MBB, get(BccOpc)).addMBB(TBB)
+    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
   BuildMI(&MBB, get(BOpc)).addMBB(FBB);
   return 2;
 }
@@ -452,6 +456,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
   if (Opc == ARM::B || Opc == ARM::tB) {
     MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
     MI->addImmOperand(Pred[0].getImmedValue());
+    MI->addRegOperand(Pred[1].getReg(), false);
     return true;
   }
 
@@ -459,6 +464,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
   if (PIdx != -1) {
     MachineOperand &PMO = MI->getOperand(PIdx);
     PMO.setImm(Pred[0].getImmedValue());
+    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
     return true;
   }
   return false;
@@ -467,7 +473,7 @@ bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
 bool
 ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
                                 const std::vector<MachineOperand> &Pred2) const{
-  if (Pred1.size() > 1 || Pred2.size() > 1)
+  if (Pred1.size() > 2 || Pred2.size() > 2)
     return false;
 
   ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImmedValue();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index f9d760b874b..4d773343ab2 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -66,7 +66,8 @@ namespace {
 
     SmallVector<MachineBasicBlock::iterator, 4>
     MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex, unsigned Base,
-                 int Opcode, unsigned Size, ARMCC::CondCodes Pred,
+                 int Opcode, unsigned Size,
+                 ARMCC::CondCodes Pred, unsigned PredReg,
                  unsigned Scratch, MemOpQueue &MemOps);
 
     void AdvanceRS(MachineBasicBlock &MBB, MemOpQueue &MemOps);
@@ -112,7 +113,7 @@ static int getLoadStoreMultipleOpcode(int Opcode) {
 /// It returns true if the transformation is done. 
 static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                      int Offset, unsigned Base, bool BaseKill, int Opcode,
-                     ARMCC::CondCodes Pred, unsigned Scratch,
+                     ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
                      SmallVector<std::pair<unsigned, bool>, 8> &Regs,
                      const TargetInstrInfo *TII) {
   // Only a single register to load / store. Don't bother.
@@ -156,7 +157,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
       return false;  // Probably not worth it then.
 
     BuildMI(MBB, MBBI, TII->get(BaseOpc), NewBase)
-      .addReg(Base, false, false, BaseKill).addImm(ImmedOffset).addImm(Pred);
+      .addReg(Base, false, false, BaseKill).addImm(ImmedOffset)
+      .addImm(Pred).addReg(PredReg);
     Base = NewBase;
     BaseKill = true;  // New base is always killed right its use.
   }
@@ -166,10 +168,10 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
   Opcode = getLoadStoreMultipleOpcode(Opcode);
   MachineInstrBuilder MIB = (isAM4)
     ? BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
-        .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred)
+        .addImm(ARM_AM::getAM4ModeImm(Mode)).addImm(Pred).addReg(PredReg)
     : BuildMI(MBB, MBBI, TII->get(Opcode)).addReg(Base, false, false, BaseKill)
         .addImm(ARM_AM::getAM5Opc(Mode, false, isDPR ? NumRegs<<1 : NumRegs))
-        .addImm(Pred);
+        .addImm(Pred).addReg(PredReg);
   for (unsigned i = 0; i != NumRegs; ++i)
     MIB = MIB.addReg(Regs[i].first, isDef, false, Regs[i].second);
 
@@ -181,8 +183,8 @@ static bool mergeOps(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
 SmallVector<MachineBasicBlock::iterator, 4>
 ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
                               unsigned Base, int Opcode, unsigned Size,
-                              ARMCC::CondCodes Pred, unsigned Scratch,
-                              MemOpQueue &MemOps) {
+                              ARMCC::CondCodes Pred, unsigned PredReg,
+                              unsigned Scratch, MemOpQueue &MemOps) {
   SmallVector<MachineBasicBlock::iterator, 4> Merges;
   bool isAM4 = Opcode == ARM::LDR || Opcode == ARM::STR;
   int Offset = MemOps[SIndex].Offset;
@@ -209,8 +211,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
       PRegNum = RegNum;
     } else {
       // Can't merge this in. Try merge the earlier ones first.
-      if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, Scratch,
-                   Regs, TII)) {
+      if (mergeOps(MBB, ++Loc, SOffset, Base, false, Opcode, Pred, PredReg,
+                   Scratch, Regs, TII)) {
         Merges.push_back(prior(Loc));
         for (unsigned j = SIndex; j < i; ++j) {
           MBB.erase(MemOps[j].MBBI);
@@ -218,7 +220,7 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
         }
       }
       SmallVector<MachineBasicBlock::iterator, 4> Merges2 =
-        MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, Scratch, MemOps);
+        MergeLDR_STR(MBB, i, Base, Opcode, Size, Pred, PredReg, Scratch,MemOps);
       Merges.append(Merges2.begin(), Merges2.end());
       return Merges;
     }
@@ -230,8 +232,8 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
   }
 
   bool BaseKill = Loc->findRegisterUseOperandIdx(Base, true) != -1;
-  if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, Scratch,
-               Regs, TII)) {
+  if (mergeOps(MBB, ++Loc, SOffset, Base, BaseKill, Opcode, Pred, PredReg,
+               Scratch, Regs, TII)) {
     Merges.push_back(prior(Loc));
     for (unsigned i = SIndex, e = MemOps.size(); i != e; ++i) {
       MBB.erase(MemOps[i].MBBI);
@@ -243,29 +245,41 @@ ARMLoadStoreOpt::MergeLDR_STR(MachineBasicBlock &MBB, unsigned SIndex,
 }
 
 /// getInstrPredicate - If instruction is predicated, returns its predicate
-/// condition, otherwise returns AL.
-static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI) {
+/// condition, otherwise returns AL. It also returns the condition code
+/// register by reference.
+static ARMCC::CondCodes getInstrPredicate(MachineInstr *MI, unsigned &PredReg) {
   int PIdx = MI->findFirstPredOperandIdx();
-  return PIdx == -1 ? ARMCC::AL
-                    : (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
+  if (PIdx == -1) {
+    PredReg = 0;
+    return ARMCC::AL;
+  }
+
+  PredReg = MI->getOperand(PIdx+1).getReg();
+  return (ARMCC::CondCodes)MI->getOperand(PIdx).getImmedValue();
 }
 
 static inline bool isMatchingDecrement(MachineInstr *MI, unsigned Base,
-                                       unsigned Bytes, ARMCC::CondCodes Pred) {
+                                       unsigned Bytes, ARMCC::CondCodes Pred,
+                                       unsigned PredReg) {
+  unsigned MyPredReg = 0;
   return (MI && MI->getOpcode() == ARM::SUBri &&
           MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
           ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
-          getInstrPredicate(MI) == Pred);
+          getInstrPredicate(MI, MyPredReg) == Pred &&
+          MyPredReg == PredReg);
 }
 
 static inline bool isMatchingIncrement(MachineInstr *MI, unsigned Base,
-                                       unsigned Bytes, ARMCC::CondCodes Pred) {
+                                       unsigned Bytes, ARMCC::CondCodes Pred,
+                                       unsigned PredReg) {
+  unsigned MyPredReg = 0;
   return (MI && MI->getOpcode() == ARM::ADDri &&
           MI->getOperand(0).getReg() == Base &&
           MI->getOperand(1).getReg() == Base &&
           ARM_AM::getAM2Offset(MI->getOperand(2).getImm()) == Bytes &&
-          getInstrPredicate(MI) == Pred);
+          getInstrPredicate(MI, MyPredReg) == Pred &&
+          MyPredReg == PredReg);
 }
 
 static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
@@ -281,7 +295,7 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
     return 8;
   case ARM::LDM:
   case ARM::STM:
-    return (MI->getNumOperands() - 3) * 4;
+    return (MI->getNumOperands() - 4) * 4;
   case ARM::FLDMS:
   case ARM::FSTMS:
   case ARM::FLDMD:
@@ -307,7 +321,8 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
   MachineInstr *MI = MBBI;
   unsigned Base = MI->getOperand(0).getReg();
   unsigned Bytes = getLSMultipleTransferSize(MI);
-  ARMCC::CondCodes Pred = getInstrPredicate(MI);
+  unsigned PredReg = 0;
+  ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
   int Opcode = MI->getOpcode();
   bool isAM4 = Opcode == ARM::LDM || Opcode == ARM::STM;
 
@@ -326,12 +341,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.begin()) {
       MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
+          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::db, true));
         MBB.erase(PrevMBBI);
         return true;
       } else if (Mode == ARM_AM::ib &&
-                 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
+                 isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(ARM_AM::da, true));
         MBB.erase(PrevMBBI);
         return true;
@@ -341,12 +356,12 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.end()) {
       MachineBasicBlock::iterator NextMBBI = next(MBBI);
       if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
-          isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
+          isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
         MBB.erase(NextMBBI);
         return true;
       } else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
-                 isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
+                 isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
         MBB.erase(NextMBBI);
         return true;
@@ -362,7 +377,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.begin()) {
       MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
+          isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::db, true, Offset));
         MBB.erase(PrevMBBI);
         return true;
@@ -372,7 +387,7 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
     if (MBBI != MBB.end()) {
       MachineBasicBlock::iterator NextMBBI = next(MBBI);
       if (Mode == ARM_AM::ia &&
-          isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
+          isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
         MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
         MBB.erase(NextMBBI);
       }
@@ -430,17 +445,19 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
   if (isLd && MI->getOperand(0).getReg() == Base)
     return false;
 
-  ARMCC::CondCodes Pred = getInstrPredicate(MI);
+  unsigned PredReg = 0;
+  ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
   bool DoMerge = false;
   ARM_AM::AddrOpc AddSub = ARM_AM::add;
   unsigned NewOpc = 0;
   if (MBBI != MBB.begin()) {
     MachineBasicBlock::iterator PrevMBBI = prior(MBBI);
-    if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred)) {
+    if (isMatchingDecrement(PrevMBBI, Base, Bytes, Pred, PredReg)) {
       DoMerge = true;
       AddSub = ARM_AM::sub;
       NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
-    } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes, Pred)) {
+    } else if (isAM2 && isMatchingIncrement(PrevMBBI, Base, Bytes,
+                                            Pred, PredReg)) {
       DoMerge = true;
       NewOpc = getPreIndexedLoadStoreOpcode(Opcode);
     }
@@ -450,11 +467,11 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
 
   if (!DoMerge && MBBI != MBB.end()) {
     MachineBasicBlock::iterator NextMBBI = next(MBBI);
-    if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred)) {
+    if (isAM2 && isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
       DoMerge = true;
       AddSub = ARM_AM::sub;
       NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
-    } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred)) {
+    } else if (isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
       DoMerge = true;
       NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
     }
@@ -474,22 +491,24 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
       // LDR_PRE, LDR_POST;
       BuildMI(MBB, MBBI, TII->get(NewOpc), MI->getOperand(0).getReg())
         .addReg(Base, true)
-        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
+        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
     else
       // FLDMS, FLDMD
       BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base, false, false, BaseKill)
-        .addImm(Offset).addImm(Pred).addReg(MI->getOperand(0).getReg(), true);
+        .addImm(Offset).addImm(Pred).addReg(PredReg)
+        .addReg(MI->getOperand(0).getReg(), true);
   } else {
     MachineOperand &MO = MI->getOperand(0);
     if (isAM2)
       // STR_PRE, STR_POST;
       BuildMI(MBB, MBBI, TII->get(NewOpc), Base)
         .addReg(MO.getReg(), false, false, MO.isKill())
-        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred);
+        .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
     else
       // FSTMS, FSTMD
       BuildMI(MBB, MBBI, TII->get(NewOpc)).addReg(Base).addImm(Offset)
-        .addImm(Pred).addReg(MO.getReg(), false, false, MO.isKill());
+        .addImm(Pred).addReg(PredReg)
+        .addReg(MO.getReg(), false, false, MO.isKill());
   }
   MBB.erase(MBBI);
 
@@ -541,6 +560,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
   int CurrOpc = -1;
   unsigned CurrSize = 0;
   ARMCC::CondCodes CurrPred = ARMCC::AL;
+  unsigned CurrPredReg = 0;
   unsigned Position = 0;
 
   RS->enterBasicBlock(&MBB);
@@ -556,9 +576,10 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
       bool isAM2 = Opcode == ARM::LDR || Opcode == ARM::STR;
       unsigned Size = getLSMultipleTransferSize(MBBI);
       unsigned Base = MBBI->getOperand(1).getReg();
-      ARMCC::CondCodes Pred = getInstrPredicate(MBBI);
+      unsigned PredReg = 0;
+      ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
       const TargetInstrDescriptor *TID = MBBI->getInstrDescriptor();
-      unsigned OffField = MBBI->getOperand(TID->numOperands-2).getImm();
+      unsigned OffField = MBBI->getOperand(TID->numOperands-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {
@@ -584,6 +605,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
         CurrOpc  = Opcode;
         CurrSize = Size;
         CurrPred = Pred;
+        CurrPredReg = PredReg;
         MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
         NumMemOps++;
         Advance = true;
@@ -594,6 +616,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
         }
 
         if (CurrOpc == Opcode && CurrBase == Base && CurrPred == Pred) {
+          // No need to match PredReg.
           // Continue adding to the queue.
           if (Offset > MemOps.back().Offset) {
             MemOps.push_back(MemOpQueueEntry(Offset, Position, MBBI));
@@ -639,8 +662,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
 
         // Merge ops.
         SmallVector<MachineBasicBlock::iterator,4> MBBII =
-          MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize, CurrPred,
-                       Scratch, MemOps);
+          MergeLDR_STR(MBB, 0, CurrBase, CurrOpc, CurrSize,
+                       CurrPred, CurrPredReg, Scratch, MemOps);
 
         // Try folding preceeding/trailing base inc/dec into the generated
         // LDM/STM ops.
@@ -664,6 +687,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
       CurrOpc = -1;
       CurrSize = 0;
       CurrPred = ARMCC::AL;
+      CurrPredReg = 0;
       if (NumMemOps) {
         MemOps.clear();
         NumMemOps = 0;