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Add support for selecting 256-bit PALIGNR.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2012-01-20 05:53:00 +00:00
parent b28885057e
commit 0e2037ba2b
3 changed files with 139 additions and 25 deletions
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96
lib/Target/X86/X86ISelLowering.cpp
View File

@ -3253,35 +3253,74 @@ bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
/// isPALIGNRMask - Return true if the node specifies a shuffle of elements that
/// is suitable for input to PALIGNR.
static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT, bool hasSSSE3) {
int i, e = VT.getVectorNumElements();
if (VT.getSizeInBits() != 128)
static bool isPALIGNRMask(ArrayRef<int> Mask, EVT VT,
const X86Subtarget *Subtarget) {
if ((VT.getSizeInBits() == 128 && !Subtarget->hasSSSE3()) ||
(VT.getSizeInBits() == 256 && !Subtarget->hasAVX2()))
return false;
// Do not handle v2i64 / v2f64 shuffles with palignr.
if (e < 4 || !hasSSSE3)
unsigned NumElts = VT.getVectorNumElements();
unsigned NumLanes = VT.getSizeInBits()/128;
unsigned NumLaneElts = NumElts/NumLanes;
// Do not handle 64-bit element shuffles with palignr.
if (NumLaneElts == 2)
return false;
for (i = 0; i != e; ++i)
if (Mask[i] >= 0)
break;
for (unsigned l = 0; l != NumElts; l+=NumLaneElts) {
unsigned i;
for (i = 0; i != NumLaneElts; ++i) {
if (Mask[i+l] >= 0)
break;
}
// All undef, not a palignr.
if (i == e)
return false;
// Lane is all undef, go to next lane
if (i == NumLaneElts)
continue;
// Make sure we're shifting in the right direction.
if (Mask[i] <= i)
return false;
int Start = Mask[i+l];
int s = Mask[i] - i;
// Check the rest of the elements to see if they are consecutive.
for (++i; i != e; ++i) {
int m = Mask[i];
if (m >= 0 && m != s+i)
// Make sure its in this lane in one of the sources
if (!isUndefOrInRange(Start, l, l+NumLaneElts) &&
!isUndefOrInRange(Start, l+NumElts, l+NumElts+NumLaneElts))
return false;
// If not lane 0, then we must match lane 0
if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Start, Mask[i]+l))
return false;
// Correct second source to be contiguous with first source
if (Start >= (int)NumElts)
Start -= NumElts - NumLaneElts;
// Make sure we're shifting in the right direction.
if (Start <= (int)(i+l))
return false;
Start -= i;
// Check the rest of the elements to see if they are consecutive.
for (++i; i != NumLaneElts; ++i) {
int Idx = Mask[i+l];
// Make sure its in this lane
if (!isUndefOrInRange(Idx, l, l+NumLaneElts) &&
!isUndefOrInRange(Idx, l+NumElts, l+NumElts+NumLaneElts))
return false;
// If not lane 0, then we must match lane 0
if (l != 0 && Mask[i] >= 0 && !isUndefOrEqual(Idx, Mask[i]+l))
return false;
if (Idx >= (int)NumElts)
Idx -= NumElts - NumLaneElts;
if (!isUndefOrEqual(Idx, Start+i))
return false;
}
}
return true;
}
@ -3983,14 +4022,21 @@ unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) {
static unsigned getShufflePALIGNRImmediate(ShuffleVectorSDNode *SVOp) {
EVT VT = SVOp->getValueType(0);
unsigned EltSize = VT.getVectorElementType().getSizeInBits() >> 3;
int Val = 0;
unsigned i, e;
for (i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
unsigned NumElts = VT.getVectorNumElements();
unsigned NumLanes = VT.getSizeInBits()/128;
unsigned NumLaneElts = NumElts/NumLanes;
int Val = 0;
unsigned i;
for (i = 0; i != NumElts; ++i) {
Val = SVOp->getMaskElt(i);
if (Val >= 0)
break;
}
if (Val >= (int)NumElts)
Val -= NumElts - NumLaneElts;
assert(Val - i > 0 && "PALIGNR imm should be positive");
return (Val - i) * EltSize;
}
@ -6626,7 +6672,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
// inlined here right now to enable us to directly emit target specific
// nodes, and remove one by one until they don't return Op anymore.
if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3()))
if (isPALIGNRMask(M, VT, Subtarget))
return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2,
getShufflePALIGNRImmediate(SVOp),
DAG);
@ -11089,7 +11135,7 @@ X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
isPSHUFDMask(M, VT) ||
isPSHUFHWMask(M, VT) ||
isPSHUFLWMask(M, VT) ||
isPALIGNRMask(M, VT, Subtarget->hasSSSE3()) ||
isPALIGNRMask(M, VT, Subtarget) ||
isUNPCKLMask(M, VT, Subtarget->hasAVX2()) ||
isUNPCKHMask(M, VT, Subtarget->hasAVX2()) ||
isUNPCKL_v_undef_Mask(M, VT, Subtarget->hasAVX2()) ||

11
lib/Target/X86/X86InstrSSE.td
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@ -5476,6 +5476,17 @@ let Predicates = [HasAVX2] in
let Constraints = "$src1 = $dst", Predicates = [HasSSSE3] in
defm PALIGN : ssse3_palign<"palignr">;
let Predicates = [HasAVX2] in {
def : Pat<(v8i32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
def : Pat<(v8f32 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
def : Pat<(v16i16 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
def : Pat<(v32i8 (X86PAlign VR256:$src1, VR256:$src2, (i8 imm:$imm))),
(VPALIGNR256rr VR256:$src2, VR256:$src1, imm:$imm)>;
}
let Predicates = [HasAVX] in {
def : Pat<(v4i32 (X86PAlign VR128:$src1, VR128:$src2, (i8 imm:$imm))),
(VPALIGNR128rr VR128:$src2, VR128:$src1, imm:$imm)>;

57
test/CodeGen/X86/avx2-palignr.ll Normal file
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@ -0,0 +1,57 @@
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
define <8 x i32> @test1(<8 x i32> %A, <8 x i32> %B) nounwind {
; CHECK: test1:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
ret <8 x i32> %C
}
define <8 x i32> @test2(<8 x i32> %A, <8 x i32> %B) nounwind {
; CHECK: test2:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 undef, i32 12>
ret <8 x i32> %C
}
define <8 x i32> @test3(<8 x i32> %A, <8 x i32> %B) nounwind {
; CHECK: test3:
; CHECK: vpalignr $4
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
ret <8 x i32> %C
}
;
define <8 x i32> @test4(<8 x i32> %A, <8 x i32> %B) nounwind {
; CHECK: test4:
; CHECK: vpalignr $8
%C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 10, i32 11, i32 undef, i32 1, i32 14, i32 15, i32 4, i32 5>
ret <8 x i32> %C
}
define <16 x i16> @test5(<16 x i16> %A, <16 x i16> %B) nounwind {
; CHECK: test5:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 undef, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
ret <16 x i16> %C
}
define <16 x i16> @test6(<16 x i16> %A, <16 x i16> %B) nounwind {
; CHECK: test6:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
ret <16 x i16> %C
}
define <16 x i16> @test7(<16 x i16> %A, <16 x i16> %B) nounwind {
; CHECK: test7:
; CHECK: vpalignr $6
%C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i16> %C
}
define <32 x i8> @test8(<32 x i8> %A, <32 x i8> %B) nounwind {
; CHECK: test8:
; CHECK: palignr $5
%C = shufflevector <32 x i8> %A, <32 x i8> %B, <32 x i32> <i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52>
ret <32 x i8> %C
}