From 0e4044c233d10596578df35bae2483fbe4e8a507 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Mon, 5 Aug 2013 11:00:53 +0000 Subject: [PATCH] [SystemZ] Add LOAD AND TEST instructions Just the definitions and MC support. The next patch uses them for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/SystemZ/SystemZInstrInfo.td | 13 +++ test/MC/Disassembler/SystemZ/insns.txt | 126 +++++++++++++++++++++++++ test/MC/SystemZ/insn-bad.s | 24 +++++ test/MC/SystemZ/insn-good.s | 96 +++++++++++++++++++ 4 files changed, 259 insertions(+) diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 748539aa5b6..58fb662efdd 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -223,6 +223,10 @@ let neverHasSideEffects = 1 in { def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>; def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>; } +let Defs = [CC], CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in { + def LTR : UnaryRR <"lt", 0x12, null_frag, GR32, GR32>; + def LTGR : UnaryRRE<"ltg", 0xB902, null_frag, GR64, GR64>; +} // Move on condition. let isCodeGenOnly = 1, Uses = [CC] in { @@ -265,6 +269,11 @@ let canFoldAsLoad = 1, SimpleBDXLoad = 1 in { [(set GR128:$dst, (load bdxaddr20only128:$src))]>; } } +let Defs = [CC], CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in { + def LT : UnaryRXY<"lt", 0xE312, load, GR32, 4>; + def LTG : UnaryRXY<"ltg", 0xE302, load, GR64, 8>; +} + let canFoldAsLoad = 1 in { def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>; def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>; @@ -358,6 +367,8 @@ let neverHasSideEffects = 1 in { def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>; def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>; } +let Defs = [CC], CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in + def LTGFR : UnaryRRE<"ltgf", 0xB912, null_frag, GR64, GR64>; // Match 32-to-64-bit sign extensions in which the source is already // in a 64-bit register. @@ -375,6 +386,8 @@ def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>; def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>; def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>; def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>; +let Defs = [CC], CCValues = 0xE, CCHasZero = 1, CCHasOrder = 1 in + def LTGF : UnaryRXY<"ltgf", 0xE332, sextloadi32, GR64, 4>; // If the sign of a load-extend operation doesn't matter, use the signed ones. // There's not really much to choose between the sign and zero extensions, diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index fa30bd31a0e..de65a68c376 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -3613,6 +3613,132 @@ # CHECK: l %r15, 0 0x58 0xf0 0x00 0x00 +# CHECK: lt %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x12 + +# CHECK: lt %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x12 + +# CHECK: lt %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x12 + +# CHECK: lt %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x12 + +# CHECK: lt %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x12 + +# CHECK: lt %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x12 + +# CHECK: lt %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x12 + +# CHECK: lt %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x12 + +# CHECK: lt %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x12 + +# CHECK: lt %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x12 + +# CHECK: ltg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x02 + +# CHECK: ltg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x02 + +# CHECK: ltg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x02 + +# CHECK: ltg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x02 + +# CHECK: ltg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x02 + +# CHECK: ltg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x02 + +# CHECK: ltg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x02 + +# CHECK: ltg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x02 + +# CHECK: ltg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x02 + +# CHECK: ltg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x02 + +# CHECK: ltgf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x32 + +# CHECK: ltgf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x32 + +# CHECK: ltgf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x32 + +# CHECK: ltgf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x32 + +# CHECK: ltgf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x32 + +# CHECK: ltgf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x32 + +# CHECK: ltgf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x32 + +# CHECK: ltgf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x32 + +# CHECK: ltgfr %r0, %r9 +0xb9 0x12 0x00 0x09 + +# CHECK: ltgfr %r0, %r15 +0xb9 0x12 0x00 0x0f + +# CHECK: ltgfr %r15, %r0 +0xb9 0x12 0x00 0xf0 + +# CHECK: ltgfr %r15, %r9 +0xb9 0x12 0x00 0xf9 + +# CHECK: ltgr %r0, %r9 +0xb9 0x02 0x00 0x09 + +# CHECK: ltgr %r0, %r15 +0xb9 0x02 0x00 0x0f + +# CHECK: ltgr %r15, %r0 +0xb9 0x02 0x00 0xf0 + +# CHECK: ltgr %r15, %r9 +0xb9 0x02 0x00 0xf9 + +# CHECK: ltr %r0, %r9 +0x12 0x09 + +# CHECK: ltr %r0, %r15 +0x12 0x0f + +# CHECK: ltr %r15, %r0 +0x12 0xf0 + +# CHECK: ltr %r15, %r9 +0x12 0xf9 + # CHECK: lxr %f0, %f8 0xb3 0x65 0x00 0x08 diff --git a/test/MC/SystemZ/insn-bad.s b/test/MC/SystemZ/insn-bad.s index eab11d1dd24..a3218edb941 100644 --- a/test/MC/SystemZ/insn-bad.s +++ b/test/MC/SystemZ/insn-bad.s @@ -1592,6 +1592,30 @@ lrvg %r0, -524289 lrvg %r0, 524288 +#CHECK: error: invalid operand +#CHECK: lt %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lt %r0, 524288 + + lt %r0, -524289 + lt %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ltg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ltg %r0, 524288 + + ltg %r0, -524289 + ltg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: ltgf %r0, -524289 +#CHECK: error: invalid operand +#CHECK: ltgf %r0, 524288 + + ltgf %r0, -524289 + ltgf %r0, 524288 + #CHECK: error: invalid register pair #CHECK: lxr %f0, %f2 #CHECK: error: invalid register pair diff --git a/test/MC/SystemZ/insn-good.s b/test/MC/SystemZ/insn-good.s index 874c1c6d0e5..5ddae83a7a7 100644 --- a/test/MC/SystemZ/insn-good.s +++ b/test/MC/SystemZ/insn-good.s @@ -4806,6 +4806,102 @@ lrvr %r7,%r8 lrvr %r15,%r15 +#CHECK: lt %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x12] +#CHECK: lt %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x12] +#CHECK: lt %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x12] +#CHECK: lt %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x12] +#CHECK: lt %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x12] +#CHECK: lt %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x12] +#CHECK: lt %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x12] +#CHECK: lt %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x12] +#CHECK: lt %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x12] +#CHECK: lt %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x12] + + lt %r0, -524288 + lt %r0, -1 + lt %r0, 0 + lt %r0, 1 + lt %r0, 524287 + lt %r0, 0(%r1) + lt %r0, 0(%r15) + lt %r0, 524287(%r1,%r15) + lt %r0, 524287(%r15,%r1) + lt %r15, 0 + +#CHECK: ltg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x02] +#CHECK: ltg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x02] +#CHECK: ltg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x02] +#CHECK: ltg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x02] +#CHECK: ltg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x02] +#CHECK: ltg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x02] +#CHECK: ltg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x02] +#CHECK: ltg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x02] +#CHECK: ltg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x02] +#CHECK: ltg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x02] + + ltg %r0, -524288 + ltg %r0, -1 + ltg %r0, 0 + ltg %r0, 1 + ltg %r0, 524287 + ltg %r0, 0(%r1) + ltg %r0, 0(%r15) + ltg %r0, 524287(%r1,%r15) + ltg %r0, 524287(%r15,%r1) + ltg %r15, 0 + +#CHECK: ltgf %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x32] +#CHECK: ltgf %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x32] +#CHECK: ltgf %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x32] +#CHECK: ltgf %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x32] +#CHECK: ltgf %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x32] +#CHECK: ltgf %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x32] +#CHECK: ltgf %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x32] +#CHECK: ltgf %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x32] +#CHECK: ltgf %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x32] +#CHECK: ltgf %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x32] + + ltgf %r0, -524288 + ltgf %r0, -1 + ltgf %r0, 0 + ltgf %r0, 1 + ltgf %r0, 524287 + ltgf %r0, 0(%r1) + ltgf %r0, 0(%r15) + ltgf %r0, 524287(%r1,%r15) + ltgf %r0, 524287(%r15,%r1) + ltgf %r15, 0 + +#CHECK: ltgfr %r0, %r9 # encoding: [0xb9,0x12,0x00,0x09] +#CHECK: ltgfr %r0, %r15 # encoding: [0xb9,0x12,0x00,0x0f] +#CHECK: ltgfr %r15, %r0 # encoding: [0xb9,0x12,0x00,0xf0] +#CHECK: ltgfr %r15, %r9 # encoding: [0xb9,0x12,0x00,0xf9] + + ltgfr %r0,%r9 + ltgfr %r0,%r15 + ltgfr %r15,%r0 + ltgfr %r15,%r9 + +#CHECK: ltgr %r0, %r9 # encoding: [0xb9,0x02,0x00,0x09] +#CHECK: ltgr %r0, %r15 # encoding: [0xb9,0x02,0x00,0x0f] +#CHECK: ltgr %r15, %r0 # encoding: [0xb9,0x02,0x00,0xf0] +#CHECK: ltgr %r15, %r9 # encoding: [0xb9,0x02,0x00,0xf9] + + ltgr %r0,%r9 + ltgr %r0,%r15 + ltgr %r15,%r0 + ltgr %r15,%r9 + +#CHECK: ltr %r0, %r9 # encoding: [0x12,0x09] +#CHECK: ltr %r0, %r15 # encoding: [0x12,0x0f] +#CHECK: ltr %r15, %r0 # encoding: [0x12,0xf0] +#CHECK: ltr %r15, %r9 # encoding: [0x12,0xf9] + + ltr %r0,%r9 + ltr %r0,%r15 + ltr %r15,%r0 + ltr %r15,%r9 + #CHECK: lxr %f0, %f8 # encoding: [0xb3,0x65,0x00,0x08] #CHECK: lxr %f0, %f13 # encoding: [0xb3,0x65,0x00,0x0d] #CHECK: lxr %f13, %f0 # encoding: [0xb3,0x65,0x00,0xd0]