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https://github.com/c64scene-ar/llvm-6502.git
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eliminate the dead IsPCRel argument.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95858 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -83,8 +83,8 @@ public:
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}
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}
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}
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}
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void EmitDisplacementField(const MCOperand &Disp, bool IsPCRel,
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void EmitDisplacementField(const MCOperand &Disp, unsigned &CurByte,
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unsigned &CurByte, raw_ostream &OS,
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raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const;
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SmallVectorImpl<MCFixup> &Fixups) const;
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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@ -136,7 +136,7 @@ static bool isDisp8(int Value) {
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}
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}
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void X86MCCodeEmitter::
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void X86MCCodeEmitter::
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EmitDisplacementField(const MCOperand &DispOp, bool IsPCRel,
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EmitDisplacementField(const MCOperand &DispOp,
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unsigned &CurByte, raw_ostream &OS,
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unsigned &CurByte, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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SmallVectorImpl<MCFixup> &Fixups) const {
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// If this is a simple integer displacement that doesn't require a relocation,
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// If this is a simple integer displacement that doesn't require a relocation,
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@ -172,9 +172,6 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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const MCOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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unsigned BaseReg = Base.getReg();
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// FIXME: Eliminate!
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bool IsPCRel = false;
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// Determine whether a SIB byte is needed.
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// Determine whether a SIB byte is needed.
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// If no BaseReg, issue a RIP relative instruction only if the MCE can
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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// resolve addresses on-the-fly, otherwise use SIB (Intel Manual 2A, table
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@ -190,7 +187,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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if (BaseReg == 0 || // [disp32] in X86-32 mode
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if (BaseReg == 0 || // [disp32] in X86-32 mode
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BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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BaseReg == X86::RIP) { // [disp32+RIP] in X86-64 mode
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EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
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EmitByte(ModRMByte(0, RegOpcodeField, 5), CurByte, OS);
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EmitDisplacementField(Disp, true, CurByte, OS, Fixups);
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EmitDisplacementField(Disp, CurByte, OS, Fixups);
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return;
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return;
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}
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}
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@ -214,7 +211,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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// Otherwise, emit the most general non-SIB encoding: [REG+disp32]
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// Otherwise, emit the most general non-SIB encoding: [REG+disp32]
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitByte(ModRMByte(2, RegOpcodeField, BaseRegNo), CurByte, OS);
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EmitDisplacementField(Disp, IsPCRel, CurByte, OS, Fixups);
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EmitDisplacementField(Disp, CurByte, OS, Fixups);
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return;
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return;
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}
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}
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@ -271,7 +268,7 @@ void X86MCCodeEmitter::EmitMemModRMByte(const MCInst &MI, unsigned Op,
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if (ForceDisp8)
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if (ForceDisp8)
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EmitConstant(Disp.getImm(), 1, CurByte, OS);
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EmitConstant(Disp.getImm(), 1, CurByte, OS);
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else if (ForceDisp32 || Disp.getImm() != 0)
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else if (ForceDisp32 || Disp.getImm() != 0)
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EmitDisplacementField(Disp, IsPCRel, CurByte, OS, Fixups);
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EmitDisplacementField(Disp, CurByte, OS, Fixups);
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}
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}
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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/// DetermineREXPrefix - Determine if the MCInst has to be encoded with a X86-64
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