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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-01 19:29:22 +00:00
Minor cleanups. No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120372 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -136,6 +136,8 @@ def tADJCALLSTACKDOWN :
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Requires<[IsThumb, IsThumb1Only]>;
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Requires<[IsThumb, IsThumb1Only]>;
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}
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}
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// T1Disassembly - A simple class to make encoding some disassembly patterns
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// easier and less verbose.
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class T1Disassembly<bits<2> op1, bits<8> op2>
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class T1Disassembly<bits<2> op1, bits<8> op2>
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: T1Encoding<0b101111> {
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: T1Encoding<0b101111> {
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let Inst{9-8} = op1;
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let Inst{9-8} = op1;
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@ -205,7 +207,8 @@ def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
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[/* For disassembly only; pattern left blank */]>,
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[/* For disassembly only; pattern left blank */]>,
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T1Misc<0b0110011> {
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T1Misc<0b0110011> {
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// A8.6.38 & B6.1.1
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// A8.6.38 & B6.1.1
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let Inst{3} = 0; // FIXME: Finish encoding.
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let Inst{3} = 0;
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// FIXME: Finish encoding.
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}
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}
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// For both thumb1 and thumb2.
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// For both thumb1 and thumb2.
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@ -213,13 +216,13 @@ let isNotDuplicable = 1, isCodeGenOnly = 1 in
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
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T1Special<{0,0,?,?}> {
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T1Special<{0,0,?,?}> {
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// A8.6.6 Rm = pc
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// A8.6.6
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bits<3> dst;
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bits<3> dst;
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let Inst{6-3} = 0b1111;
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let Inst{6-3} = 0b1111; // Rm = pc
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let Inst{2-0} = dst;
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let Inst{2-0} = dst;
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}
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}
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// PC relative add.
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// PC relative add (ADR).
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
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def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
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"add\t$dst, pc, $rhs", []>,
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"add\t$dst, pc, $rhs", []>,
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T1Encoding<{1,0,1,0,0,?}> {
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T1Encoding<{1,0,1,0,0,?}> {
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@ -1265,14 +1268,13 @@ def tLEApcrelJT : T1I<(outs tGPR:$Rd),
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//
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//
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// __aeabi_read_tp preserves the registers r1-r3.
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// __aeabi_read_tp preserves the registers r1-r3.
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let isCall = 1, Defs = [R0, LR], Uses = [SP] in {
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let isCall = 1, Defs = [R0, LR], Uses = [SP] in
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def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
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def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
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"bl\t__aeabi_read_tp",
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"bl\t__aeabi_read_tp",
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[(set R0, ARMthread_pointer)]> {
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[(set R0, ARMthread_pointer)]> {
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// Encoding is 0xf7fffffe.
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// Encoding is 0xf7fffffe.
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let Inst = 0xf7fffffe;
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let Inst = 0xf7fffffe;
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}
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}
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}
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// SJLJ Exception handling intrinsics
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// SJLJ Exception handling intrinsics
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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// eh_sjlj_setjmp() is an instruction sequence to store the return
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@ -1286,23 +1288,20 @@ let isCall = 1, Defs = [R0, LR], Uses = [SP] in {
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// doing so, we also cause the prologue/epilogue code to actively preserve
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// doing so, we also cause the prologue/epilogue code to actively preserve
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// all of the callee-saved resgisters, which is exactly what we want.
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// all of the callee-saved resgisters, which is exactly what we want.
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// $val is a scratch register for our use.
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// $val is a scratch register for our use.
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let Defs =
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let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
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[ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
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hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
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isBarrier = 1, isCodeGenOnly = 1 in {
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def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
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def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
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AddrModeNone, SizeSpecial, NoItinerary, "","",
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AddrModeNone, SizeSpecial, NoItinerary, "","",
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[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
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[(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
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}
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// FIXME: Non-Darwin version(s)
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// FIXME: Non-Darwin version(s)
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let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
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let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
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Defs = [ R7, LR, SP ] in {
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Defs = [ R7, LR, SP ] in
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def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
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def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
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AddrModeNone, SizeSpecial, IndexModeNone,
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AddrModeNone, SizeSpecial, IndexModeNone,
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Pseudo, NoItinerary, "", "",
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Pseudo, NoItinerary, "", "",
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[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
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[(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
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Requires<[IsThumb, IsDarwin]>;
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Requires<[IsThumb, IsDarwin]>;
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}
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Non-Instruction Patterns
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// Non-Instruction Patterns
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